SN74ALS244C-1

ACTIVE

Octal Buffers/Line Drivers with 3-State Outputs

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Octal Buffers/Line Drivers with 3-State Outputs

SN74ALS244C-1

ACTIVE

Product details

Parameters

Technology Family ALS VCC (Min) (V) 4.75 VCC (Max) (V) 5.25 Channels (#) 8 IOL (Max) (mA) 48 IOH (Max) (mA) -15 Input type Bipolar Output type 3-State Features Very high speed (tpd 5-10ns) Data rate (Mbps) 150 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SOP (NS) 20 98 mm² 12.6 x 7.8 open-in-new Find other Non-Inverting buffer/driver

Features

  • 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers
  • pnp Inputs Reduce dc Loading
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs

 

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Description

These octal buffers and line drivers are designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. With the ´ALS240A, ´ALS241C, ´AS240A, and ´AS241A, these devices provide the choice of selected combinations of inverting outputs, symmetrical active-low output-enable () inputs, and complementary OE and inputs.

The -1 version of SN74ALS244C is identical to the standard version, except that the recommended maximum IOL for the -1 version is 48 mA. There is no -1 version of the SN54ALS244C.

The SN54ALS244C and SN54AS244A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS244C and SN74AS244A are characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Datasheet Octal Buffers And Line Drivers With 3-State Outputs datasheet (Rev. C) Aug. 01, 1995
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDAM066.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SO (NS) 20 View options
SOIC (DW) 20 View options

Ordering & quality

Support & training

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