SN74ALS873B

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Dual 4-Bit D-Type Latches With 3-State Outputs

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Product details

Parameters

Technology Family ALS Input type Bipolar Output type 3-State VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 Clock Frequency (Max) (MHz) 75 ICC (uA) 32000 IOL (Max) (mA) 24 IOH (Max) (mA) -2.6 Features High speed (tpd 10-50ns) Rating Catalog open-in-new Find other D-type latch

Package | Pins | Size

SOIC (DW) 24 160 mm² 15.5 x 10.3 open-in-new Find other D-type latch

Features

  • 3-State Buffer-Type Outputs Drive Bus Lines Directly
  • Bus-Structured Pinout
  • Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs

 

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Description

These dual 4-bit D-type latches feature 3-state outputs designed specifically for bus driving. These devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The dual 4-bit latches are transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs in true form, according to the function table. When LE is low, the outputs are latched. When the clear () input goes low, the Q outputs go low independently of LE. The outputs are in the high-impedance state when the output-enable () input is at a high logic level.

The SN54ALS873B and SN54AS873A are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS873B and SN74AS873A are characterized for operation from 0°C to 70°C.

 

 

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Technical documentation

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Type Title Date
* Datasheet Dual 4-Bit D-Type Latches With 3-State Outputs datasheet (Rev. D) Aug. 01, 1995
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes Advanced Schottky (ALS and AS) Logic Families Aug. 01, 1995

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SDAM026.ZIP (11 KB) - IBIS Model

CAD/CAE symbols

Package Pins Download
SOIC (DW) 24 View options

Ordering & quality

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