Available in the Texas Instruments NanoFree™ Package
Optimized for 1.8-V Operation and Is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
I_off Supports Partial-Power-Down Mode
Operation
Sub-1-V Operable
Max t_pd of 1.9 ns at 1.8 V
Low Power Consumption, 10-µA Max I_CC
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

NanoFree is a trademark of Texas Instruments.

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Description

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V V_CC, but is designed specifically for 1.65-V to 1.95-V V_CC operation.

When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using I_off. The I_off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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	Type	Title	Date
*	Datasheet	SN74AUC1G80 datasheet (Rev. K)	Jan. 11, 2007
	Selection guide	Little Logic Guide 2018 (Rev. G)	Jul. 06, 2018
	Selection guide	Logic Guide (Rev. AB)	Jun. 12, 2017
	Application note	How to Select Little Logic (Rev. A)	Jul. 26, 2016
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	Dec. 02, 2015
	Application note	Power-Up Behavior of Clocked Devices (Rev. A)	Feb. 06, 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	Jan. 16, 2007
	More literature	Design Summary for WCSP Little Logic (Rev. B)	Nov. 04, 2004
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	Jul. 08, 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	Jun. 22, 2004
	User guide	Signal Switch Data Book (Rev. A)	Nov. 14, 2003
	More literature	Logic Cross-Reference (Rev. A)	Oct. 07, 2003
	Application note	Designing With TI Ultra-Low-Voltage CMOS (AUC) Octals and Widebus Devices	Mar. 21, 2003
	User guide	AUC Data Book, January 2003 (Rev. A)	Jan. 01, 2003
	Application note	Texas Instruments Little Logic Application Report	Nov. 01, 2002
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	Aug. 29, 2002
	More literature	Standard Linear & Logic for PCs, Servers & Motherboards	Jun. 13, 2002
	More literature	STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS	Mar. 27, 2002
	More literature	AUC Product Brochure (Rev. A)	Mar. 18, 2002