This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
When data at the data (D) input meets the setup time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
NanoFree is a trademark of Texas Instruments.
|Part number||Order||Technology Family||Input type||Output type||VCC (Min) (V)||VCC (Max) (V)||Channels (#)||Clock Frequency (Max) (MHz)||ICC (uA)||IOL (Max) (mA)||IOH (Max) (mA)||Features||Rating||Package Group|
Ultra high speed (tpd <5ns)
Over-voltage tolerant inputs
Partial power down (Ioff)
DSBGA | 5
SC70 | 5
SOT-23 | 5