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SN74AXC2T245 ACTIVE Dual-bit, 2-DIR pin dual-supply bus transceiver w/ configurable voltage translation, 3-state output Pin-to-pin upgrade with a wider voltage range and improved performance
Dual-Bit, 2-DIR pin Dual-Supply Bus Transceiver w/ Configurable Voltage Translation, 3-State Output

SN74AVC2T245

ACTIVE

Product details

Technology Family AVC Applications JTAG Bits (#) 2 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 1.2 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
Technology Family AVC Applications JTAG Bits (#) 2 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Vout (Min) (V) 1.2 Vout (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog
UQFN (RSW) 10 3 mm² 1.8 x 1.4
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to
    3.6 V Power-Supply Range
  • I/Os Are 4.6 V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at
    GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1500 V Charged-Device Model (C101)
  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to
    3.6 V Power-Supply Range
  • I/Os Are 4.6 V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at
    GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1500 V Charged-Device Model (C101)

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Data sheet SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs datasheet (Rev. D) 22 Feb 2016
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
User guide SN74AXC2T-SMALLPKGEVM Evaluation module user's guide 04 Jun 2019
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
More literature LCD Module Interface Application Clip 09 May 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

Design & development

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Simulation model

SN74AVC2T245 IBIS Model

SCEM532.ZIP (64 KB) - IBIS Model
Simulation model

HSPICE Model for SN74AVC2T245

SCEM533.ZIP (102 KB) - HSpice Model
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UQFN (RSW) 10 View options

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