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Dual-Bit, 2-DIR pin Dual-Supply Bus Transceiver w/ Configurable Voltage Translation, 3-State Output

SN74AVC2T245

ACTIVE

Product details

Parameters

Technology Family AVC Applications JTAG Bits (#) 2 High input voltage (Min) (Vih) 0.78 High input voltage (Max) (Vih) 3.6 Output voltage (Min) (V) 1.2 Output voltage (Max) (V) 3.6 IOH (Max) (mA) -12 IOL (Max) (mA) 12 Rating Catalog open-in-new Find other Direction-controlled voltage translators

Package | Pins | Size

UQFN (RSW) 10 3 mm² 1.8 x 1.4 open-in-new Find other Direction-controlled voltage translators

Features

  • Each Channel Has Independent Direction Control
  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to
    3.6 V Power-Supply Range
  • I/Os Are 4.6 V Tolerant
  • Ioff Supports Partial-Power-Down Mode Operation
  • VCC Isolation Feature - If Either VCC Input is at
    GND, Both Ports are in High-Impedance State
  • Typical Data Rates
    • 500 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 320 Mbps (Translate to 2.5 V or 1.8 V)
    • 280 Mbps (Translate to 1.5 V)
    • 240 Mbps (Translate to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 5000 V Human-Body Model (A114-A)
    • 200 V Machine Model (A115-A)
    • 1500 V Charged-Device Model (C101)
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Description

This dual-bit noninverting bus transceiver uses two separate configurable power-supply rails. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronous communication between two data buses. The logic levels of the direction-control (DIR) input and the output-enable (OE) activate either the B-port outputs or the A-port outputs or place both output ports into the high-impedance mode . The device transmits data from the A bus to the B bus when the B-port outputs are activated and from the B bus to the A bus when the A-port outputs are activated. The input circuitry on both A and B ports always is active and must have a logic HIGH or LOW level applied to prevent excess ICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, and OE) are supplied by VCCA.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The VCC isolation feature ensures that if either VCC input is at GND, both ports are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE must be connected to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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Technical documentation

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Type Title Date
* Datasheet SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs datasheet (Rev. D) Feb. 22, 2016
Selection guides Voltage translation buying guide Jun. 13, 2019
User guides SN74AXC2T-SMALLPKGEVM Evaluation module user's guide Jun. 04, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) Apr. 30, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. A) Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
More literature LCD Module Interface Application Clip May 09, 2003
User guides AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) Aug. 20, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application notes 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application notes Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) Jul. 07, 1999
Application notes AVC Logic Family Technology and Applications (Rev. A) Aug. 26, 1998

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
20
Description
This EVM is designed to support DTM and RSW packages for the AXC and LVC family of DIR controlled bidirectional devices. The AXC and AVC devices belong to the low voltage direction controlled translation family with operating voltage from 0.65V to 3.6V (AXC) and 1.2 to 3.6 (AVC) with 12mA of drive (...)
Features
  • Pre-populated with the SN74AXC2T45DTM package
  • Demonstrates the small package technology of TI 
  • Ground port for each header pin supports high speed measurement
  • DIR pin; have the option of 10K ohm resistor pullup or pulldown
DEVELOPMENT KITS Download
document-generic User guide
699
Description

The K2G Evaluation Module (EVM) enables developers to immediately start evaluating the 66AK2Gx - 600MHz processor, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive applications.  Similar to (...)

Features
  • 66AK2G02 C66x DSP+ARM A15 Processor at 600MHz
  • 2-GByte DDR3L with ECC
  • TPS659118 PMIC
  • Audio and Serial expansion headers
  • Processor SDK Linux and TI-RTOS support
  • Supports Gigabit Ethernet
DEVELOPMENT KITS Download
document-generic User guide
699
Description

The EVMK2GX (also known as "K2G") 1GHz Evaluation Module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

Features
  • 66AK2G12 C66x DSP+ARM A15 Processor at 1GHz
  • 2-GByte DDR3L with ECC
  • TPS65911A PMIC
  • Audio and serial expansion headers
  • Processor SDK Linux and TI-RTOS support
DEVELOPMENT KITS Download
document-generic User guide
1049
Description

The K2G 1GHz High Secure Evaluation Module (EVM) enables developers to start  evaluating and testing the programming of the  high secure developmental version of the  66AK2Gx processor, and to accelerate the next stage of secure boot product development of audio and industrial real (...)

Features
  • 66AK2G12 C66x DSP+ARM A15 Processor at 1GHz
  • 2-GByte DDR3L with ECC
  • TPS65911A PMIC
  • Audio and serial expansion headers
  • Processor SDK Linux and TI-RTOS support

Design tools & simulation

SIMULATION MODELS Download
SCEM532.ZIP (64 KB) - IBIS Model
SIMULATION MODELS Download
SCEM533.ZIP (102 KB) - HSpice Model

Reference designs

REFERENCE DESIGNS Download
EnDat 2.2 System Reference Design
TIDEP0050 The TIDEP0050 TI Design implements the EnDat 2.2 Master protocol stack and hardware interface solution based on the HEIDENHAIN EnDat 2.2 standard for position or rotary encoders. The design is composed of the EnDat 2.2 Master protocol stack, half-duplex communications using RS485 transceivers and (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Ultrasonic Distance Measurement using the TLV320AIC3268 miniDSP CODEC Reference Design
TIDA-00403 The TIDA-00403 reference design uses off-the-shelf EVMs for ultrasonic distance measurement solutions using algorithms within the TLV320AIC3268 miniDSP. In conjunction with TI’s PurePath Studio design suite, a robust and user configurable ultrasonic distance measurement system can be designed (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
UQFN (RSW) 10 View options

Ordering & quality

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