SN74HC259

ACTIVE

8-Bit Addressable Latches

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Product details

Parameters

Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Bits (#) 8 Voltage (Nom) (V) 6 F @ nom voltage (Max) (MHz) 28 ICC @ nom voltage (Max) (mA) 0.08 Propagation delay (Max) (ns) 28 IOL (Max) (mA) 5.2 IOH (Max) (mA) -5.2 3-state output No Operating temperature range (C) -40 to 85 open-in-new Find other Other latch

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 5 x 4.4 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Other latch

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current Inverting Outputs Drive Up To 10 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 14 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • 8-Bit Parallel-Out Storage Register Performs Serial-to-Parallel Conversion With Storage
  • Asynchronous Parallel Clear
  • Active-High Decoder
  • Enable Input Simplifies Expansion
  • Expandable for n-Bit Applications
  • Four Distinct Functional Modes

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Description

These 8-bit addressable latches are designed for general-purpose storage applications in digital systems. Specific uses include working registers, serial-holding registers, and active-high decoders or demultiplexers. They are multifunctional devices capable of storing single-line data in eight addressable latches and being a 1-of-8 decoder or demultiplexer with active-high outputs.

Four distinct modes of operation are selectable by controlling the clear (CLR)\ and enable (G)\ inputs. In the addressable-latch mode, data at the data-in terminal is written into the addressed latch. The addressed latch follows the data input, with all unaddressed latches remaining in their previous states. In the memory mode, all latches remain in their previous states and are unaffected by the data or address inputs. To eliminate the possibility of entering erroneous data in the latches, G\ should be held high (inactive) while the address lines are changing. In the 1-of-8 decoding or demultiplexing mode, the addressed output follows the level of the D input with all other outputs low. In the clear mode, all outputs are low and unaffected by the address and data inputs.

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Technical documentation

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Type Title Date
* Datasheet SN54HC259, SN74HC259 datasheet (Rev. E) Sep. 15, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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