SN74HC563

ACTIVE

Octal Transparent D-Type Latches With 3-State Outputs

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Product details

Parameters

Channels (#) 8 Technology Family HC VCC (Min) (V) 2 VCC (Max) (V) 6 Input type Standard CMOS Output type 3-State Clock Frequency (Max) (MHz) 28 IOL (Max) (mA) 7.8 IOH (Max) (mA) -7.8 ICC (Max) (uA) 80 Features Balanced outputs, High speed (tpd 10-50ns), Positive input clamp diode, Inverting output, Flow-through pinout open-in-new Find other D-type latch

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 open-in-new Find other D-type latch

Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • High-Current 3-State Outputs Drive Bus Lines Directly or Up To 15 LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 21 ns
  • ±6-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Bus-Structured Pinout

open-in-new Find other D-type latch

Description

These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

While the latch-enable (LE) input is high, the Q\ outputs follow the complements of the data (D) inputs. When LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.

A buffered output-enable (OE)\ input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines without interface or pullup components.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

OE\ does not affect internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

open-in-new Find other D-type latch
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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet SN54HC563, SN74HC563 datasheet (Rev. C) Mar. 18, 2003
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application notes Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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