The ’HCT257 devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (OE)\ input is at the high logic level.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| Type | Title | Date | ||
|---|---|---|---|---|
| * | Data sheet | SN54HCT257, SN74HCT257 datasheet (Rev. D) | 15 Sep 2003 | |
| More literature | Implications of Slow or Floating CMOS Inputs (Rev. E) | 26 Jul 2021 | ||
| Selection guide | Logic Guide (Rev. AB) | 12 Jun 2017 | ||
| More literature | Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) | 02 Dec 2015 | ||
| User guide | LOGIC Pocket Data Book (Rev. B) | 16 Jan 2007 | ||
| More literature | Semiconductor Packing Material Electrostatic Discharge (ESD) Protection | 08 Jul 2004 | ||
| User guide | Signal Switch Data Book (Rev. A) | 14 Nov 2003 | ||
| More literature | TI IBIS File Creation, Validation, and Distribution Processes | 29 Aug 2002 | ||
| More literature | CMOS Power Consumption and CPD Calculation (Rev. B) | 01 Jun 1997 | ||
| More literature | Designing With Logic (Rev. C) | 01 Jun 1997 | ||
| More literature | SN54/74HCT CMOS Logic Family Applications and Restrictions | 01 May 1996 | ||
| More literature | Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc | 01 Apr 1996 |
For additional terms or required resources, click any title below to view the detail page where available.
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.
| Package | Pins | Download |
|---|---|---|
| PDIP (N) | 16 | View options |
| SOIC (D) | 16 | View options |
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