SN74LS14

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6-ch, 4.75-V to 5.25-V bipolar inverters with Schmitt-Trigger inputs

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Product details

Parameters

Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Number of channels (#) 6 IOL (Max) (mA) 8 IOH (Max) (mA) -0.4 ICC (Max) (uA) 21000 Input type Schmitt-Trigger Output type Push-Pull Features High speed (tpd 10-50ns), Input clamp diode Rating Catalog open-in-new Find other Inverting buffers & drivers

Package | Pins | Size

PDIP (N) 14 181 mm² 19.3 x 9.4 SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 open-in-new Find other Inverting buffers & drivers

Features

  • Operation From Very Slow Edges
  • Improved Line-Receiving Characteristics
  • High Noise Immunity
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Description

Each circuit in SNx414 and SNx4LS14 functions as an inverter. However, because of the Schmitt-Trigger action, they have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

These circuits are temperature compensated and can be triggered from the slowest of input ramps and still give clean, jitter-free output signals.

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Technical documentation

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Type Title Date
* Data sheet SNx414 and SNx4LS14 Hex Schmitt-Trigger Inverters datasheet (Rev. C) Nov. 30, 2016
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Understanding Schmitt Triggers Sep. 21, 2011
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SDLM005C.ZIP (6 KB) - IBIS Model
SIMULATION MODEL Download
SDLM046.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 14 View options
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options

Ordering & quality

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  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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