Product details

Function Counter Bits (#) 4 Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull Features High speed (tpd 10-50ns)
Function Counter Bits (#) 4 Technology Family LS Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull Features High speed (tpd 10-50ns)
PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8
  • Cascading Circuitry Provided Internally
  • Synchronous Operation
  • Individual Preset to Each Flip-Flop
  • Fully Independent Clear Input
  • Cascading Circuitry Provided Internally
  • Synchronous Operation
  • Individual Preset to Each Flip-Flop
  • Fully Independent Clear Input

These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high.

All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers etc., required for long words.

These counters are designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.

The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high.

All four counters are fully programmable; that is, each output may be preset to either level by entering the desired data at the data inputs while the load input is low. The output will change to agree with the data inputs independently of the count pulses. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs.

A clear input has been provided which forces all outputs to the low level when a high level is applied. The clear function is independent of the count and load inputs. The clear, count, and load inputs are buffered to lower the drive requirements. This reduces the number of clock drivers etc., required for long words.

These counters are designed to be cascaded without the need for external circuitry. Both borrow and carry outputs are available to cascade both the up- and down-counting functions. The borrow output produces a pulse equal in width to the count-down input when the counter underflows. Similarly, the carry output produces a pulse equal in width to the count-up input when an overflow condition exists. The counters can then be easily cascaded by feeding the borrow and carry outputs to the count-down and count-up inputs respectively of the succeeding counter.

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Technical documentation

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Type Title Date
* Data sheet Synchronous 4-Bit Up/Down Counters (Dual Clock With Clear) datasheet 01 Mar 1988
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options

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