Product details

Technology Family LS Bits (#) 15 Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull ICC (Max) (uA) 50000 IOL (Max) (mA) 24 IOH (Max) (mA) -1.2
Technology Family LS Bits (#) 15 Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Input type Bipolar Output type Push-Pull ICC (Max) (uA) 50000 IOL (Max) (mA) 24 IOH (Max) (mA) -1.2
PDIP (N) 16 181 mm² 19.3 x 9.4
  • Count Divider Chain
  • Digitally Programmable from 22 to 2n
    (n = 31 for SN74LS292 , n = 15 for SN74LS294)
  • Useable Frequency Range from DC to 30 MHz
  • Easily Expandable
  • Count Divider Chain
  • Digitally Programmable from 22 to 2n
    (n = 31 for SN74LS292 , n = 15 for SN74LS294)
  • Useable Frequency Range from DC to 30 MHz
  • Easily Expandable

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210 gives a period of 1.024 ms, 220 gives a period of 1.05 sec, 226 gives a period of 1.12 min, and 231 gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

The SN74LS29x devices are programmable frequency dividers and digital timers contain 31 flip-flops plus 30 gates (in SN74LS292) or 15 flip-flops plus 29 gates (in SN74LS294) on a single chip. The count modulo is under digital control of the inputs provided.

Both types feature an active-low CLR clear input to initialize the state of all flip-flops. To facilitate the incoming inspection, test points are provided (TP1, TP2, and TP3 on the SN74LS292, and TP on the SN74LS294). These test points are not intended to drive system loads. Both types feature two clock inputs; either one may be used for clock gating.

A brief look at the digital timing capabilities of the SN74LS292 shows that with a 1-MHz input frequency, programming for 210 gives a period of 1.024 ms, 220 gives a period of 1.05 sec, 226 gives a period of 1.12 min, and 231 gives a period of 35.79 min.

These devices are easily cascadable, giving limitless possibilities to achievable timing delays.

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Technical documentation

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Type Title Date
* Data sheet SN74LS29x Programmable Frequency Dividers and Digital Timers datasheet (Rev. A) PDF | HTML 07 Jan 2016
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Designing with the SN54/74LS123 (Rev. A) 01 Mar 1997
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996

Design & development

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Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

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PDIP (N) 16 View options

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