Product details

Number of channels (#) 2 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Technology Family LV-A Input type Schmitt-Trigger Output type Push-Pull ICC (uA) 20 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable
Number of channels (#) 2 Supply voltage (Min) (V) 2 Supply voltage (Max) (V) 5.5 Technology Family LV-A Input type Schmitt-Trigger Output type Push-Pull ICC (uA) 20 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Features Balanced outputs, High speed (tpd 10-50ns), Over-voltage tolerant inputs, Partial power down (Ioff), Retriggerable
SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 SSOP (DB) 16 48 mm² 6.2 x 7.8 TSSOP (PW) 16 22 mm² 5 x 4.4 TSSOP (PW) 16 22 mm² 4.4 x 5 TVSOP (DGV) 16 23 mm² 3.6 x 6.4 VQFN (RGY) 16 14 mm² 4 x 3.5
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 2-V to 5.5-V VCC Operation
  • Maximum tpd of 11 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2.3 V at VCC = 3.3 V, TA = 25°C
  • Support Mixed-Mode Voltage Operation on
    All Ports
  • Schmitt-Trigger Circuitry on A, B, and CLR Inputs
    for Slow Input Transition Rates
  • Edge Triggered From Active-High or
    Active-Low Gated Logic Inputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Retriggerable for Very Long Output Pulses,
    up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • Glitch-Free Power-Up Reset on Outputs
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class 11
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V VCC operation.

These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method, the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.

The output pulse duration is programmable by selecting external resistance and capacitance values. The external timing capacitor must be connected between Cext and Rext/Cext (positive) and an external resistor connected between Rext/Cext and VCC. To obtain variable pulse durations, connect an external variable resistance between Rext/Cext and VCC. The output pulse duration also can be reduced by taking CLR low.

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Technical documentation

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Type Title Date
* Data sheet SNx4LV123A Dual Retriggerable Monostable Multivibrators With Schmitt-Trigger Inputs datasheet (Rev. Q) 31 Aug 2015
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) 13 Mar 2020
Selection guide Logic Guide (Rev. AB) 12 Jun 2017

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

In stock
Limit: 5
Evaluation board

14-24-NL-LOGIC-EVM — Generic 14 through 24 pin non-leaded package evaluation module

Flexible EVM designed to support any logic or translation device that has a BQA, BQB, RGY (14-24 pin), RSV, RJW, or RHL package.
In stock
Limit: 10
Simulation model

SN74LV123A IBIS Model (Rev. A)

SCEM125A.ZIP (21 KB) - IBIS Model
Simulation model

SN74LV123A PSpice Model (Rev. C)

SCEM569C.ZIP (384 KB) - PSpice Model
Simulation model

HSPICE Model for SN74LV123A

SCLJ019.ZIP (111 KB) - HSpice Model
Package Pins Download
SO (NS) 16 View options
SOIC (D) 16 View options
SSOP (DB) 16 View options
TSSOP (PW) 16 View options
TVSOP (DGV) 16 View options
VQFN (RGY) 16 View options

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  • Ongoing reliability monitoring

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