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Product details

Parameters

Technology Family LV-A VCC (Min) (V) 2 VCC (Max) (V) 5.5 Bits (#) 4 Voltage (Nom) (V) 2.5, 3.3, 5 F @ nom voltage (Max) (MHz) 65, 105 ICC @ nom voltage (Max) (mA) 0.02 tpd @ nom Voltage (Max) (ns) 16.5 IOL (Max) (mA) 12 IOH (Max) (mA) -12 Function Counter Product type Binary Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Counter, arithmetic & parity function ICs

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 SOP (NS) 14 80 mm² 10.2 x 7.8 SSOP (DB) 14 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 TVSOP (DGV) 14 23 mm² 3.6 x 6.4 open-in-new Find other Counter, arithmetic & parity function ICs

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 10 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down-Mode Operation
  • Dual 4-Bit Binary Counters With Individual Clocks
  • Direct Clear for Each 4-Bit Counter
  • Can Significantly Improve System Densities by Reducing Counter Package Count by 50 Percent
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Description

The ’LV393A devices contain eight flip-flops and additional gating to implement two individual 4-bit counters in a single package. These devices are designed for 2-V to 5.5-V VCC operation.

These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)\ input. These devices change state on the negative-going transition of the CLK\ pulse. N-bit binary counters can be implemented with each package, providing the capability of divide by 256. The ’LV393A devices have parallel outputs from each counter stage so that any submultiple of the input count frequency is available for system timing signals.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

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Technical documentation

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Type Title Date
* Datasheet SN54LV393A, SN74LV393A datasheet (Rev. D) Apr. 20, 2005

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Reference designs

REFERENCE DESIGNS Download
16-Bit, 1MSPS Multiplexed Data Acquisition Reference Design
TIPD169 This design is for a 16-bit 1MSPS single-ended, multiplexed data acquisition system (DAQ) for dc inputs. The system is composed of a 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC), SAR ADC driver, reference driver, and multiplexer. The design shows the process to (...)
document-generic Schematic document-generic User guide
Design files

CAD/CAE symbols

Package Pins Download
SO (NS) 14 View options
SOIC (D) 14 View options
SSOP (DB) 14 View options
TSSOP (PW) 14 View options
TVSOP (DGV) 14 View options

Ordering & quality

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