SN74LV574A Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs | TI.com

SN74LV574A
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs - SN74LV574A
Datasheet
 

Description

The ’LV574A devices are octal edge-triggered D-type flip-flops designed for 2-V to 5.5-V VCC operation.

These devices feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs.

A buffered output-enable (OE)\ input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE\ does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down.

Features

  • 2-V to 5.5-V VCC Operation
  • Max tpd of 10 ns at 5 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
       >2.3 V at VCC = 3.3 V, TA = 25°C
  • Supports Mixed-Mode Signal Operation on All Ports
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

Parametrics

Compare all products in D-type flip-flop Email Download to Excel
Part number Order Technology Family Input type Output type VCC (Min) (V) VCC (Max) (V) IOL (Max) (mA) IOH (Max) (mA) Rating Package Group
SN74LV574A Order now LV-A     CMOS     CMOS     2     5.5     50     -50     Catalog     SOIC | 20
SO | 20
SSOP | 20
TSSOP | 20
TVSOP | 20
VQFN | 20