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SN74LVC2G04

ACTIVE

2-ch, 1.65-V to 5.5-V inverters

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Data sheet

SN74LVC2G04

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Supply current (max) (µA) 10 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Rating Catalog Operating temperature range (°C) -40 to 125
SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G04 device performs the Boolean function Y = A.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This dual inverter is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G04 device performs the Boolean function Y = A.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC2G04 Dual Inverter Gate datasheet (Rev. N) PDF | HTML Aug 31, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

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Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Simulation model

SN74LVC2G04 Behavioral SPICE Model

SCEM623.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC2G04 IBIS Model (Rev. A)

SCEM248 (244 KB) - IBIS model
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Package Pins CAD symbols, footprints & 3D models
SOT-SC70 (DCK) 6 Ultra Librarian
SOT-23 (DBV) 6 Ultra Librarian
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DSBGA (YZP) 6 Ultra Librarian
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