SN74LVC2G74

ACTIVE

Single Positive-Edge-Triggered D-Type Flip-Flop with Clear and Preset

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Product details

Parameters

Number of channels (#) 1 Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 200 IOL (Max) (mA) 32 IOH (Max) (mA) -32 ICC (Max) (uA) 10 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff) open-in-new Find other D-type flip-flops

Package | Pins | Size

DSBGA (YZP) 8 3 mm² .927 x 1.928 SSOP (DCT) 8 8 mm² 2.95 x 2.80 VSSOP (DCU) 8 6 mm² 2 x 3.1 open-in-new Find other D-type flip-flops

Features

  • Available in the Texas Instruments NanoFree™ package
  • Supports 5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • Maximum tpd of 5.9 ns at 3.3 V
  • Low power consumption, 10 µA maximum ICC
  • ±24 mA output drive at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000 V human-body model
    • 200 V machine model
    • 1000 V charged-device model
open-in-new Find other D-type flip-flops

Description

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

open-in-new Find other D-type flip-flops
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Technical documentation

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Type Title Date
* Data sheet SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. Q) Sep. 14, 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) Jul. 26, 2021
Selection guide Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note How to Select Little Logic (Rev. A) Jul. 26, 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) Feb. 06, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application note Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
User guide Signal Switch Data Book (Rev. A) Nov. 14, 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits Nov. 06, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) Dec. 18, 2002
Application note Texas Instruments Little Logic Application Report Nov. 01, 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards Jun. 13, 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) May 22, 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices May 10, 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS Mar. 27, 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application note LVC Characterization Information Dec. 01, 1996
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide Sep. 01, 1996
Application note Understanding Advanced Bus-Interface Products Design Guide May 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
10
Description
Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODEL Download
SCEJ238.ZIP (91 KB) - HSpice Model
SIMULATION MODEL Download
SCEM282.ZIP (51 KB) - IBIS Model

Reference designs

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REFERENCE DESIGNS Download
Bidirectional 400-V/12-V DC/DC Converter Reference Design
TIDM-BIDIR-400-12 The Bidirectional 400V-12V DC/DC Converter Reference Design is a microcontroller-based implementation of an isolated bi-directional DC-DC converter.  A phase shifted full-bridge (PSFB) with synchronous rectification controls power flow from a 400V bus/battery to the 12V battery in step-down (...)
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REFERENCE DESIGNS Download
C2000™ Solar DC/DC Converter with Maximum Power Point Tracking (MPPT)
TIDM-SOLAR-DCDC This design is a digitally-controlled, solar DC/DC converter with maximum power point tracking (MPPT), for use in central or string solar inverters. It is a companion to TIDM-SOLAR-ONEPHINV, a grid-tied, single phase, DC/AC inverter. Together, TIDM-SOLAR-DCDC and TIDM-SOLAR-ONEPHINV comprise a  (...)
document-generic Schematic

CAD/CAE symbols

Package Pins Download
DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

Ordering & quality

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  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Support & training

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