Product details

Number of channels (#) 1 Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 200 IOL (Max) (mA) 32 IOH (Max) (mA) -32 ICC (Max) (uA) 10 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)
Number of channels (#) 1 Technology Family LVC Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 5.5 Input type Standard CMOS Output type Push-Pull Clock Frequency (Max) (MHz) 200 IOL (Max) (mA) 32 IOH (Max) (mA) -32 ICC (Max) (uA) 10 Features Balanced outputs, Very high speed (tpd 5-10ns), Over-voltage tolerant inputs, Partial power down (Ioff)
DSBGA (YZP) 8 3 mm² .927 x 1.928 SSOP (DCT) 8 8 mm² 2.95 x 2.80 VSSOP (DCU) 8 6 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • Maximum tpd of 5.9 ns at 3.3 V
  • Low power consumption, 10 µA maximum ICC
  • ±24 mA output drive at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000 V human-body model
    • 200 V machine model
    • 1000 V charged-device model
  • Available in the Texas Instruments NanoFree™ package
  • Supports 5 V VCC operation
  • Inputs accept voltages to 5.5 V
  • Maximum tpd of 5.9 ns at 3.3 V
  • Low power consumption, 10 µA maximum ICC
  • ±24 mA output drive at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100 mA Per JESD 78, class II
  • ESD protection exceeds JESD 22
    • 2000 V human-body model
    • 200 V machine model
    • 1000 V charged-device model

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single positive-edge-triggered D-type flip-flop is designed for 1.65 V to 5.5 V VCC operation.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop With Clear and Preset datasheet (Rev. Q) 14 Sep 2021
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Power-Up Behavior of Clocked Devices (Rev. A) 06 Feb 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note LVC Characterization Information 01 Dec 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
Application note Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
In stock
Limit: 5
Simulation model

HSPICE MODEL OF SN74LVC2G74

SCEJ238.ZIP (91 KB) - HSpice Model
Simulation model

SN74LVC2G74 IBIS Model

SCEM282.ZIP (51 KB) - IBIS Model
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DSBGA (YZP) 8 View options
SM8 (DCT) 8 View options
VSSOP (DCU) 8 View options

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