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ARM MPU with Integrated HIPERFACE DSL Master Interface Reference Design
TIDEP0035
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
This product has been released to the market and is available for purchase. For some products, newer alternatives may be available.
See the Important Notice and Disclaimer covering reference designs and other TI resources.
Key Document
- ARM MPU With Integrated HIPERFACE DSL Master Interface Design Guide (Rev. B)
(PDF 782 KB)
07 Oct 2016
Description
Implementation of HIPERFACE DSL Master protocol on Industrial Communication Sub-System (PRU-ICSS). The two wire interface allows for integration of position feedback wires into motor cable. Complete solution consists of AM437x PRU-ICSS firmware and TIDA-00177 transceiver reference design.
Features
- Hiperface DSL master protocol with register compatible interface to existing FPGA IP core
- Programmable approach using ICSS_L concurrently with DS filter and Industrial Ethernet (Single Chip Drive)
- Internal and external sync pulse sources
- Supports cable length of up to 100 meter
- Line delay compensation
- 8x oversampling with sample edge detection
- Line diagnostics – quality monitor
See the Important Notice and Disclaimer covering reference designs and other TI resources.
