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SN74LVCH32373A

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32-bit transparent D-type latch with 3-state outputs

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Data sheet

SN74LVCH32373A

ACTIVE
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Product details

Number of channels 32 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
Number of channels 32 Technology family LVC Input type Standard CMOS Output type 3-State Clock frequency (max) (MHz) 100 IOL (max) (mA) 24 IOH (max) (mA) -24 Supply current (max) (µA) 40 Features Balanced outputs, Flow-through pinout, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Operating temperature range (°C) -40 to 85 Rating Catalog
NFBGA (NMJ) 96 74.25 mm² (13.5 mm × 5.5 mm)
  • Member of the Texas Instruments Widebus+™ Family
  • Operates from 1.65 V to 3.6 V
  • Inputs accept voltages to 5.5 V
  • Max tpd of 4.2 ns at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down mode operation
  • Supports mixed-mode signal operation (5-V Input and output voltages with 3.3-V VCC)
  • Bus hold on data inputs eliminates the need for external pullup/pulldown resistors
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
  • Member of the Texas Instruments Widebus+™ Family
  • Operates from 1.65 V to 3.6 V
  • Inputs accept voltages to 5.5 V
  • Max tpd of 4.2 ns at 3.3 V
  • Typical VOLP (output ground bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (output VOH undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff supports partial-power-down mode operation
  • Supports mixed-mode signal operation (5-V Input and output voltages with 3.3-V VCC)
  • Bus hold on data inputs eliminates the need for external pullup/pulldown resistors
  • Latch-up performance exceeds 250 mA per JESD 17
  • ESD protection exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

This 32-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH32373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVCH32373A datasheet (Rev. E) Jul 21, 2020
Application note Power-Up Behavior of Clocked Devices (Rev. B) PDF | HTML Dec 15, 2022
Application note An Overview of Bus-Hold Circuit and the Applications (Rev. B) Sep 17, 2018

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Simulation model

SN74LVCH32373A IBIS Model

SCEM117.ZIP (16 KB) - IBIS model
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NFBGA (NMJ) 96 Ultra Librarian
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