Product details

Number of I/Os 18 Features 1-MHz maximum frequency, Configuration registers, Interrupt pin, Reset pin Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Addresses 1 Rating Catalog Frequency (Max) (kHz) 1000 Operating temperature range (C) -40 to 85
Number of I/Os 18 Features 1-MHz maximum frequency, Configuration registers, Interrupt pin, Reset pin Supply voltage (Min) (V) 1.65 Supply voltage (Max) (V) 3.6 Addresses 1 Rating Catalog Frequency (Max) (kHz) 1000 Operating temperature range (C) -40 to 85
DSBGA (YFP) 25 0 mm² 2 x 2
  • Operating Power-Supply Voltage Range of 1.65 V to 3.6 V
  • 18 GPIOs Configurable as Inputs or Outputs
  • ESD Protection Exceeds JESD 22 on Non-GPIO Pins
    • 2000-V Human Body Model (A114-A)
    • 1000-V Charged Device Model (C101)
  • Low Standby (Idle) Current Consumption: 3 µA
  • Supports 1-MHz Fast Mode Plus I2C Bus
  • Open-Drain Active-Low Interrupt Output, Asserted When Key is Pressed
    or Key is Released
  • Selectable Debounce Time of 50 µs
  • Schmitt-Trigger Action Allows Slow Input Transition and
    Better Switching Noise Immunity at the SCL and SDA Inputs:
    Typical Vhys at 1.8 V is 0.18 V
  • Latch-Up Performance Exceeds 200 mA Per JESD 78, Class II
  • Very Small Package
    • WCSP (YFP): 2 mm × 2 mm; 0.4 mm pitch
  • Operating Power-Supply Voltage Range of 1.65 V to 3.6 V
  • 18 GPIOs Configurable as Inputs or Outputs
  • ESD Protection Exceeds JESD 22 on Non-GPIO Pins
    • 2000-V Human Body Model (A114-A)
    • 1000-V Charged Device Model (C101)
  • Low Standby (Idle) Current Consumption: 3 µA
  • Supports 1-MHz Fast Mode Plus I2C Bus
  • Open-Drain Active-Low Interrupt Output, Asserted When Key is Pressed
    or Key is Released
  • Selectable Debounce Time of 50 µs
  • Schmitt-Trigger Action Allows Slow Input Transition and
    Better Switching Noise Immunity at the SCL and SDA Inputs:
    Typical Vhys at 1.8 V is 0.18 V
  • Latch-Up Performance Exceeds 200 mA Per JESD 78, Class II
  • Very Small Package
    • WCSP (YFP): 2 mm × 2 mm; 0.4 mm pitch

The TCA6418E is a 18 channel GPIO expansion device with integrated ESD protection. It can operate from 1.65 V to 3.6 V and has 18 general purpose inputs/outputs (GPIO) that can be used via the I2C interface [serial clock (SCL), serial data (SDA)].

The major benefit of this device is it frees up the processor from having to individually monitor changes in multiple inputs and also frees up the GPIOs on the processor to drive other outputs.. This provides power and bandwidth savings. The TCA6418E is also ideal for usage with processors that have limited GPIOs.

The TCA6418E is a 18 channel GPIO expansion device with integrated ESD protection. It can operate from 1.65 V to 3.6 V and has 18 general purpose inputs/outputs (GPIO) that can be used via the I2C interface [serial clock (SCL), serial data (SDA)].

The major benefit of this device is it frees up the processor from having to individually monitor changes in multiple inputs and also frees up the GPIOs on the processor to drive other outputs.. This provides power and bandwidth savings. The TCA6418E is also ideal for usage with processors that have limited GPIOs.

Download

Technical documentation

star = Top documentation for this product selected by TI
No results found. Please clear your search and try again.
View all 6
Type Title Date
* Data sheet I2C Controlled 18 Channel GPIO Expander datasheet 05 Sep 2012
Application note I2C Dynamic Addressing 25 Apr 2019
Application note Choosing the Correct I2C Device for New Designs PDF | HTML 07 Sep 2016
Application note Understanding the I2C Bus PDF | HTML 30 Jun 2015
Application note Maximum Clock Frequency of I2C Bus Using Repeaters 15 May 2015
Application note I2C Bus Pull-Up Resistor Calculation PDF | HTML 13 Feb 2015

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Simulation tool

TINA-TI — SPICE-based analog simulation program

TINA-TI provides all the conventional DC, transient and frequency domain analysis of SPICE and much more. TINA has extensive post-processing capability that allows you to format results the way you want them. Virtual instruments allow you to select input waveforms and probe circuit nodes voltages (...)
User guide: PDF
Design tool

I2C-DESIGNER — I2C designer tool

Use the I2C Designer tool to quickly resolve conflicts in addressing, voltage level and frequency in I2C based designs. Enter master and slave inputs to automatically generate an I2C tree or easily build a custom solution. This tool will help designers save time and comply with the I2C standard (...)
Package Pins Download
DSBGA (YFP) 25 View options

Ordering & quality

Information included:
  • RoHS
  • REACH
  • Device marking
  • Lead finish/Ball material
  • MSL rating/Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

TI E2E™ forums with technical support from TI engineers

Content is provided "as is" by TI and community contributors and does not constitute TI specifications. See terms of use.

If you have questions about quality, packaging or ordering TI products, see TI support. ​​​​​​​​​​​​​​

Videos