TL16C752C
Dual UART With 64-Byte FIFO
TL16C752C
- SC16C752B and XR16M752 Pin Compatible With Additional Enhancements
- Support 1.8-V, 2.5-V, 3.3-V, or 5-V Supply
- Characterized for Operation from –40°C to 85°C
- Supports up to:
- 48-MHz Oscillator Input Clock (3 Mbps) for 5-V Operation
- 32-MHz Oscillator Input Clock (2 Mbps) for 3.3-V Operation
- 24-MHz Input Clock (1.5 Mbps) for 2.5-V Operation
- 16-MHz Input Clock (1 Mbps) for 1.8-V Operation
- 64-Byte Transmit/Receive FIFO
- Software-Selectable Baud-Rate Generator
- Programmable and Selectable Transmit and Receive FIFO Trigger Levels for DMA, Interrupt Generation, and Software or Hardware Flow Control
- Software/Hardware Flow Control
- Programmable Xon and Xoff Characters With Optional Xon Any Character
- Programmable Auto-RTS and Auto-CTS-Modem Control Functions (CTS, RTS, DSR, DTR, RI, and CD)
- DMA Signaling Capability for Both Received and Transmitted Data on PN Package
- RS-485 Mode Support
- Infrared Data Association (IrDA) Capability
- Programmable Sleep Mode
- Programmable Serial Interface Characteristics
- 5, 6, 7, or 8-Bit Characters With 1, 1.5, or 2 Stop Bit Generation
- Even, Odd, or No Parity Bit Generation and Detection
- False Start Bit and Line Break Detection
- Internal Test and Loopback Capabilities
The TL16C752C is a dual universal asynchronous receiver transmitter (UART) with 64-byte FIFOs, automatic hardware and software flow control, and data rates up to 3 Mbps. The device offers enhanced features. It has a transmission Character control register (TCR) that stores received FIFO threshold level to start or stop transmission during hardware and software flow control.
With the FIFO RDY register, the software gets the status of TXRDY or RXRDY for all two ports in one access. On-chip status registers provide the user with error indications, operational status, and modem interface control. System interrupts may be tailored to meet user requirements. An internal loop-back capability allows onboard diagnostics. The TL16C752C incorporates the functionality of two UARTs, each UART having its own register set and FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms are used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C752C device.
Technical documentation
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | TL16C752C Dual UART With 64-Byte FIFO datasheet (Rev. C) | PDF | HTML | 07 Jun 2017 |
| * | Errata | Short STOP Bit Errata (Rev. A) | 08 Oct 2010 |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
- Fab location
- Assembly location