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Product details

Parameters

Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) 1.08, 1.4, 1.62, 2.64 Features Active-low enable, Manual reset, Dual output Reset threshold accuracy (%) 3.7 Output driver type/reset output Active-high, Active-low, Push-pull Time delay (ms) 180 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 1.60 x 2.90 open-in-new Find other Supervisor & reset ICs

Features

  • Minimum supply voltage of 0.75 V
  • Supply voltage supervision range:
    • 1.2 V, 1.5 V, 1.8 V (TPS312x)
    • 3 V (TPS3125 devices only)
    • Other versions on request
  • Power-on reset generator with fixed delay time of 180 ms
  • Manual reset input (TPS3123/5/6/8)
  • Watchdog timer retriggers the RESET output at VDD ≥ VIT
  • Supply current of 14 µA (Typ)
  • Small SOT23-5 package
  • Temperature range of –40°C to +85°C
  • Reset output available in Push-Pull (Active Low and High) and Open-Drain (Active-Low)

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Description

The TPS312x family of voltage supervisory circuits provides voltage monitoring down to 1.2V rails and timing supervision, primarily for DSP and processor-based systems. All devices in the family monitor the power rail and assert RESET output when the power rail is under the threshold voltage target (VIT-). The threshold voltage is programmed into the device to minimize external components. Built-in hysteresis prevents false triggering. The RESET output is not valid for supply voltage (VDD) under 0.75 V. The TPS312x family includes devices with active high output for use as disable during malfunction and active low outputs for most systems where high output indicates properly functioning system.

The TPS3123/3124/3128 also include the watchdog timer functionality to monitor timely digital pulses from the processor and issue an alert if the expected pulse does not arrive on time due to potential software freeze or hang. Such integration of supply rail monitoring and the watch dog timer feature is very helpful in always on systems, such as Factory Automation and Communications Infrastructure.

In addition the TPS3123/5/6/8 devices incorporate a manual reset input, MR, to force RESET triggered by an event unrelated to the voltage rail monitoring of the pulses monitored by the watch dog timer. A low level at MR causes RESET to become active. The TPS3124 devices do not have the input MR, but include a high-level output RESET same as the TPS3125 and TPS3126 devices.

All devices in the family are available in a 5-pin SOT23-5 package and are characterized for operation over a temperature range of –40°C to +85°C.

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Technical documentation

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Type Title Date
* Data sheet TPS312x Ultra-Low Voltage Processor Supervisory Circuits datasheet (Rev. F) Dec. 23, 2020
E-book Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
User guide TIDA-00352 Test Results Dec. 11, 2014
User guide TIDA-00309 Test Results Nov. 17, 2014
Application note Video Aggregation HD-SDI Interface Application Sheet Oct. 01, 2014
Application note Video Aggregation – Display Port Interface Application Sheet Dec. 16, 2013

Design & development

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Hardware development

EVALUATION BOARD Download
document-generic User guide
199
Description
This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Features
  • Fractional baudrate support
  • 128-byte FIFO depth

Design tools & simulation

SIMULATION TOOL Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
SCHEMATIC Download
TIDRBU6.PDF (4146 KB)
SCHEMATIC Download
TIDRC52.PDF (169 KB)
SCHEMATIC Download
TIDRC53.PDF (427 KB)
BILL OF MATERIALS (BOM) Download
TIDRBU7.PDF (184 KB)
BILL OF MATERIALS (BOM) Download
TIDRC54.PDF (236 KB)
BILL OF MATERIALS (BOM) Download
TIDRC55.PDF (283 KB)
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TIDRBU9.ZIP (298 KB)
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TIDRC59.ZIP (2759 KB)
GERBER FILE Download
TIDC764.ZIP (2361 KB)
PCB LAYOUT Download
TIDRBU8.PDF (6984 KB)
PCB LAYOUT Download
TIDRC56.PDF (1522 KB)
PCB LAYOUT Download
TIDRC57.PDF (6984 KB)

Reference designs

REFERENCE DESIGNS Download
SDI Video Aggregation Reference Design
TIDA-00352 This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309 This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SOT-23 (DBV) 5 View options

Ordering & quality

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