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Product details

Parameters

Number of supplies monitored 1 Threshold voltage 1 (Typ) (V) 1.08, 1.4, 1.62, 2.64 Features Active-low enable, Manual reset, Dual output Reset threshold accuracy (%) 3.7 Output driver type/reset output Active-high, Active-low, Push-pull Time delay (ms) 180 Rating Catalog Operating temperature range (C) -40 to 85 open-in-new Find other Supervisor & reset ICs

Package | Pins | Size

SOT-23 (DBV) 5 5 mm² 1.60 x 2.90 open-in-new Find other Supervisor & reset ICs

Features

  • Minimum Supply Voltage of 0.75 V
  • Supply Voltage Supervision Range:
    • 1.2 V, 1.5 V, 1.8 V (TPS312x)
    • 3 V (TPS3125 Devices Only)
    • Other Versions on Request
  • Power-On Reset Generator With Fixed Delay Time of 180 ms
  • Manual Reset Input (TPS3123/5/6/8)
  • Watchdog Timer Retriggers the RESET Output at VDD ≥ VIT
  • Supply Current of 14 µA (Typ)
  • Small SOT23-5 Package
  • Temperature Range of –40°C to +85°C
  • Reset Output Available in Push-Pull (Active Low and High) and Open-Drain (Active-Low)
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Description

The TPS312x family of ultralow voltage processor supervisory circuits provides circuit initialization and timing supervision, primarily for DSP and processor-based systems.

During power-on, RESET is asserted when the supply voltage (VDD) becomes higher than 0.75 V. Thereafter, the supply voltage supervisor monitors VDD and keeps RESET output active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time, td = 180 ms, starts after VDD has risen above the threshold voltage (VIT).

When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. All the devices of this family have a fixed-sense threshold voltage (VIT) set by a high precision internal voltage divider.

The TPS3123/5/6/8 devices incorporate a manual reset input, MR. A low level at MR causes RESET to become active. The TPS3124 devices do not have the input MR, but include a high-level output RESET same as the TPS3125 and TPS3126 devices. In addition, the TPS3123/4/8 have a watchdog timer that needs to be triggered periodically by a positive or negative transition at WDI. When the supervising system fails to retrigger the watchdog circuit within the time-out interval ttout= 0.8 s, RESET output becomes active for the time period (td). This event also reinitializes the watchdog timer.

The circuits are available in a 5-pin SOT23-5 package. The TPS312x devices are characterized for operation over a temperature range of –40°C to +85°C.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 8
Type Title Date
* Datasheet Ultra-Low Voltage Processor Supervisory Circuits datasheet (Rev. E) Aug. 23, 2011
White papers Voltage Supervisor and Reset ICs: Tips, Tricks and Basics Jun. 28, 2019
User guides TIDA-00352 Test Results Dec. 11, 2014
User guides TIDA-00309 Test Results Nov. 17, 2014
Application notes Video Aggregation HD-SDI Interface Application Sheet Oct. 01, 2014
Application notes Video Aggregation – Display Port Interface Application Sheet Dec. 16, 2013
Technical articles Automotive electronics design made easy Jul. 18, 2013
Technical articles John discusses benefits of LEDs in automobiles Jul. 16, 2013

Design & development

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Hardware development

EVALUATION BOARDS Download
document-generic User guide
199
Description
This EVM provides the user with the ability to evaluate the TL16C750E device and its features. The EVM includes an onboard 3.3-V LDO as well as level translation for processors which operate at a higher voltage rail.
Features
  • Fractional baudrate support
  • 128-byte FIFO depth

Design tools & simulation

SIMULATION TOOLS Download
PSpice® for TI design and simulation tool
PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Features
  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
  • Dynamic updates ensure you have access to most current device models
  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
  • (...)
BILL OF MATERIALS (BOM) Download
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BILL OF MATERIALS (BOM) Download
TIDRC54.PDF (236 KB)
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TIDRC59.ZIP (2759 KB)
GERBER FILES Download
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SCHEMATICS Download
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SCHEMATICS Download
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SCHEMATICS Download
TIDRC53.PDF (427 KB)

Reference designs

REFERENCE DESIGNS Download
SDI Video Aggregation Reference Design
TIDA-00352 This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is used (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
DisplayPort Video 4:1 Aggregation Reference Design
TIDA-00309 This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
SOT-23 (DBV) 5 View options

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