Produktdetails

Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 800 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1750 SFDR (dB) 83 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
Resolution (Bits) 16 Number of DAC channels 2 Interface type Parallel CMOS Sample/update rate (Msps) 800 Features High Performance Rating Catalog Interpolation 1x, 2x, 4x, 8x Power consumption (typ) (mW) 1750 SFDR (dB) 83 Architecture Current Sink Operating temperature range (°C) -40 to 85 Reference type Int
VQFN (RGC) 64 81 mm² (9 mm × 9 mm)
  • Dual, 16-Bit, 800 MSPS DACs
  • Dual, 16-Bit, 250 MSPS CMOS Input Data
    • 16 Sample Input FIFO
    • Flexible input data bus options
  • High Performance
    • 81 dBc ACLR WCDMA TM1 at 70 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • Selectable 2x–8x Interpolation Filters
    • Stop-band Attenuation > 80 dB
  • Complex Mixer with 32-Bit NCO
  • Digital Quadrature Modulator Correction
    • Gain, Phase and Offset Correction
  • Digital Inverse SINC Filter
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-pin 9×9mm QFN
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

  • Dual, 16-Bit, 800 MSPS DACs
  • Dual, 16-Bit, 250 MSPS CMOS Input Data
    • 16 Sample Input FIFO
    • Flexible input data bus options
  • High Performance
    • 81 dBc ACLR WCDMA TM1 at 70 MHz
  • 2x-32x Clock Multiplying PLL/VCO
  • Selectable 2x–8x Interpolation Filters
    • Stop-band Attenuation > 80 dB
  • Complex Mixer with 32-Bit NCO
  • Digital Quadrature Modulator Correction
    • Gain, Phase and Offset Correction
  • Digital Inverse SINC Filter
  • 3- or 4-Wire Serial Control Interface
  • On Chip 1.2-V Reference
  • Differential Scalable Output: 2 to 20 mA
  • Package: 64-pin 9×9mm QFN
  • APPLICATIONS
    • Cellular Base Stations
    • Broadband Wireless Access (BWA)
    • WiMAX 802.16
    • Fixed Wireless Backhaul
    • Cable Modem Termination System (CMTS)

The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt 16-Bit, 800 MSPS 2x–8x Interpolating Dual-Channel Digital-to-Analog Converter (D datasheet (Rev. C) 19.08.2010
Analog Design Journal Q3 2009 Issue Analog Applications Journal 24.09.2018
Analog Design Journal Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs 14.07.2009
Anwendungshinweis Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28.04.2009
Anwendungshinweis Passive Terminations for Current Output DACs 10.11.2008
Anwendungshinweis CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08.06.2008
Anwendungshinweis Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02.06.2008

Design und Entwicklung

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Evaluierungsplatine

DAC5688EVM — DAC5688-Evaluierungsmodul

The DAC5688EVM is a circuit board that allows designers to evaluate the performance of Texas Instruments' dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with wideband LVDS data input, integrated 2x/4x/8x interpolation filters, on-board clock multiplier and PLL, 32-bit NCO and (...)

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GUI für Evaluierungsmodul (EVM)

DAC5688EVM-SW — DAC5688 EVM Software

The DAC5688 EVM software GUI allows for programming control of the DAC5688.
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GUI für Evaluierungsmodul (EVM)

SLLC420 — TSW3100EVM GUI v2.7

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Simulationsmodell

DAC5688 IBIS Model (Rev. A)

SLAC178 (107 KB) - IBIS-Modell
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Berechnungstool

SLAC170 — DAC5688 LPF Calculator

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Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
VQFN (RGC) 64 Ultra Librarian

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