Produktdetails

CPU 2 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A15 Frequency (MHz) 1500 Coprocessors 4 Arm Cortex-M4 Graphics acceleration 1 2D, 2 3D Display type 1 HDMI, 3 LCD Protocols Ethernet PCIe 1 PCIe Gen 2 Hardware accelerators Audio tracking logic, Image system processor, Image video accelerator, Viterbi decoder Features Multimedia Operating system Android, Linux, RTOS Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (ABZ) 760 529 mm² (23 mm × 23 mm)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)
  • Architecture Designed for Infotainment Applications
  • Video, Image, and Graphics Processing Support
    • Full-HD Video (1920 × 1080p, 60 fps)
    • Multiple Video Input and Video Output
    • 2D and 3D Graphics
  • Dual Arm® Cortex®-A15 Microprocessor Subsystem
  • Up to Two C66x Floating-Point VLIW DSP
    • Fully Object-Code Compatible with C67x and C64x+
    • Up to Thirty-Two 16 x 16-Bit Fixed-Point Multiplies per Cycle
  • Up to 2.5MB of On-Chip L3 RAM
  • Level 3 (L3) and Level 4 (L4) Interconnects
  • Two DDR2/DDR3/DDR3L Memory Interface (EMIF) Modules
    • Supports up to DDR2-800 and DDR3-1333
    • Up to 2GB Supported per EMIF
  • Dual ARM® Cortex®-M4 Image Processing Units (IPU)
  • Up to Two Embedded Vision Engines (EVEs)
  • Imaging Subsystem (ISS)
    • Image Signal Processor (ISP)
    • Wide Dynamic Range and Lens Distortion Correction (WDR and Mesh LDC)
    • One Camera Adaptation Layer (CAL_B)
  • IVA Subsystem
  • Display Subsystem
    • Display Controller with DMA Engine and up to Three Pipelines
    • HDMI™ Encoder: HDMI 1.4a and DVI 1.0 Compliant
  • Video Processing Engine (VPE)
  • 2D-Graphics Accelerator (BB2D) Subsystem
    • Vivante® GC320 Core
  • Dual-Core PowerVR® SGX544 3D GPU
  • Two Video Input Port (VIP) Modules
    • Support for up to Eight Multiplexed Input Ports
  • General-Purpose Memory Controller (GPMC)
  • Enhanced Direct Memory Access (EDMA) Controller
  • 2-Port Gigabit Ethernet (GMAC)
  • Sixteen 32-Bit General-Purpose Timers
  • 32-Bit MPU Watchdog Timer
  • Five Inter-Integrated Circuit (I2C) Ports
  • HDQ™/1-Wire® Interface
  • SATA Interface
  • Media Local Bus (MLB) Subsystem
  • Ten Configurable UART/IrDA/CIR Modules
  • Four Multichannel Serial Peripheral Interfaces (McSPI)
  • Quad SPI (QSPI)
  • Eight Multichannel Audio Serial Port (McASP) Modules
  • SuperSpeed USB 3.0 Dual-Role Device
  • Three High-Speed USB 2.0 Dual-Role Devices
  • Four MultiMedia Card/Secure Digital/Secure Digital Input Output Interfaces (MMC™/SD®/SDIO)
  • PCI Express® 3.0 Subsystems with Two 5-Gbps Lanes
    • One 2-Lane Gen2-Compliant Port
    • or Two 1-Lane Gen2-Compliant Ports
  • Up to Two Controller Area Network (DCAN) Modules
    • CAN 2.0B Protocol
  • Modular Controller Area Network (MCAN) Module
    • CAN 2.0B Protocol with Available FD (Flexible Data Rate) Functionality
  • Up to 247 General-Purpose I/O (GPIO) Pins
  • Real-Time Clock Subsystem (RTCSS)
  • Device Security Features
    • Hardware Crypto Accelerators and DMA
    • Firewalls
    • JTAG® Lock
    • Secure Keys
    • Secure ROM and Boot
    • Customer Programmable Keys and OTP Data
  • Power, Reset, and Clock Management
  • On-Chip Debug with CTools Technology
  • 28-nm CMOS Technology
  • 23 mm × 23 mm, 0.8-mm Pitch, 760-Pin BGA (ABZ)

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon™ extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

DRA74xP and DRA75xP (Jacinto 6 Plus) automotive applications processors are built to meet the intense processing needs of the modern digital cockpit automobile experiences.

The device enables Original-Equipment Manufacturers (OEMs) and Original-Design Manufacturers (ODMs) to quickly implement innovative connectivity technologies, speech recognition, audio streaming, and more. Jacinto 6 Plus devices bring high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The devices also combine programmable video processing with a highly integrated peripheral set.

Programmability is provided by dual-core Arm Cortex-A15 RISC CPUs with Neon extension, TI C66x VLIW floating-point DSP core, and Vision AccelerationPac (with one or more EVEs). The Arm allows developers to keep control functions separate from other algorithms programmed on the DSP and coprocessors, thus reducing the complexity of the system software.

Additionally, TI provides a complete set of development tools for the Arm, DSP, and EVE coprocessor, including C compilers and a debugging interface for visibility into source code.

Cryptographic acceleration is available in all devices. All other supported security features, including support for secure boot, debug security and support for trusted execution environment are available on High-Security (HS) devices. For more information about HS devices, contact your TI representative.

The DRA74xP and DRA75xP Jacinto 6 Plus processor family is qualified according to the AEC-Q100 standard.

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Technische Dokumentation

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Top-Dokumentation Typ Titel Format-Optionen Neueste englische Version herunterladen Datum
* Datenblatt DRA75xP, DRA74xP Infotainment Applications Processor Silicon Revision 1.0 datasheet (Rev. F) PDF | HTML 10.12.2018
* Benutzerhandbuch DRA77xP, DRA76xP, DRA75xP, DRA74xP Technical Reference Manual (Rev. D) PDF | HTML 25.05.2024
* Errata TDA2P, DRA7xxP, AM574x Package Discontinued and Redesigned (Rev. B) PDF | HTML 26.05.2026
* Errata DRA7xx Silicon Errata (Rev. B) PDF | HTML 08.09.2024
Anwendungshinweis Integrating virtual DRM between VISION SDK and PSDK on Jacinto6 SOC PDF | HTML 05.05.2021
Weitere Dokumente Building your application with security in mind (Rev. E) 28.10.2020
Anwendungshinweis IVA-HD Sharing Between VISION-SDK and PSDKLA on Jacinto6 SoC PDF | HTML 24.08.2020
Anwendungshinweis AM57x, DRA7x, and TDA2x EMIF Tools (Rev. E) 06.01.2020
Anwendungshinweis Integrating New Cameras With Video Input Port on DRA7xx SoCs PDF | HTML 11.06.2019
Anwendungshinweis Achieving Early CAN Response on DRA7xx Devices 28.11.2018
Anwendungshinweis DRA74x_75x/DRA72x Performance (Rev. A) 31.10.2018
Anwendungshinweis Audio Post Processing Engine on Jacinto™ DRA7x Family of Devices 14.09.2018
Anwendungshinweis The Implementation of YUV422 Output for SRV 02.08.2018
Anwendungshinweis MMC DLL Tuning (Rev. B) 31.07.2018
Anwendungshinweis Integrating AUTOSAR on TI SoC: Fundamentals 18.06.2018
Anwendungshinweis ECC/EDC on TDAxx (Rev. B) 13.06.2018
Anwendungshinweis Tools and Techniques to Root Case Failures in Video Capture Subsystem 12.06.2018
Anwendungshinweis Sharing VPE Between VISIONSDK and PSDKLA 04.05.2018
Anwendungshinweis Android Boot Optimization on DRA7xx Devices (Rev. A) 13.02.2018
Anwendungshinweis Flashing Utility - mflash 09.01.2018
Anwendungshinweis Using Peripheral Boot and DFU for Rapid Development on Jacinto 6 Devices (Rev. A) 30.11.2017
Anwendungshinweis Optimizing DRA7xx and TDA2xx Processors for use with Video Display SERDES (Rev. B) 07.11.2017
Anwendungshinweis A Guide to Debugging With CCS on the DRA75x, DRA74x, TDA2x and TDA3x Family of D (Rev. B) 03.11.2017
Anwendungshinweis Optimization of GPU-Based Surround View on TI’s TDA2x SoC 12.09.2017
Anwendungshinweis Using DSS Write-Back Pipeline for RGB-to-YUV Conversion on DRA7xx Devices 14.08.2017
Anwendungshinweis Software Guidelines to EMIF/DDR3 Configuration on DRA7xx Devices 12.07.2017
Whitepaper Revolutionize the automotive cockpit 02.06.2017
Anwendungshinweis Linux Boot Time Optimizations on DRA7xx Devices 31.03.2017
Anwendungshinweis Interfacing DRA75x and DRA74x Audio to Analog Codecs (Rev. A) 17.02.2017
Anwendungshinweis Early Splash Screen on DRA7x Devices 31.01.2017
Anwendungshinweis Quality of Service (QoS) Knobs for DRA74x, DRA75x & TDA2x Family of Devices (Rev. A) 15.12.2016
Anwendungshinweis Gstreamer Migration Guidelines 26.04.2016
Benutzerhandbuch Jacinto6 Android Video Encoder Software Design Specification User's Guide 21.04.2016
Benutzerhandbuch Jacinto6 Android Video Decoder Software Design Specification User's Guide 21.04.2016
Anwendungshinweis Flashing Binaries to DRA7xx Factory Boards Using DFU 14.04.2016
Anwendungshinweis Tools and Techniques for Audio Debugging 13.04.2016
Anwendungshinweis Debugging Tools and Techniques With IPC3.x 30.03.2016
Anwendungshinweis Modifying Memory Usage for IPUMM Applications Loaded IPC 3.x for DRA75x, DRA74x (Rev. A) 15.01.2016
Whitepaper Informational ADAS as Software Upgrade to Today’s Infotainment Systems 14.10.2014
Anwendungshinweis Guide to fix Perf Issues Using QoS Knobs for DRA74x, DRA75x, TDA2x & TD3x Device 13.08.2014
Whitepaper Today’s high-end infotainment soon becoming mainstream 02.06.2014

Design und Entwicklung

Lösungen für die Stromversorgung

Verfügbare Lösungen für die Stromversorgung für den DRA74P finden. TI bietet Stromversorgungslösungen für Ein-Chip-Systeme (SoCs), Prozessoren, Mikrocontroller, Sensoren und feldprogrammierbare Gate-Arrays (FPGAs) von TI und von Fremdherstellern an.

Evaluierungsplatine

J6PEVM577P — DRA7xP – Evaluierungsmodul

DRA77xP/DRA76xP-ACD ist eine Evaluierungsplattform für die Skalierbarkeit und Wiederverwendung zwischen DRA77xP- und DRA76xP-JacintoTM-Infotainment-System-on-Chips (SoCs) und basiert auf dem Jacinto-DRA77xP-SoC mit einer heterogenen, skalierbaren Architektur, die eine Mischung aus zwei (...)

Benutzerhandbuch: PDF
Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-ANDROID-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

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Software-Entwicklungskit (SDK)

PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X — PROCESSOR-SDK-LINUX-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

Unterstützte Produkte und Hardware
Software-Entwicklungskit (SDK)

PROCESSOR-SDK-RTOS-AUTOMOTIVE-DRA7X

Prozessor-SDK Linux Automotive

Das Prozessor-SDK Linux Automotive ist die grundlegende Software-Entwicklungsplattform für die Jacinto™ DRAx-Familie der Infotainment-SoCs von TI. Mit dem Software-Framework können Infotainment-Lösungen mit großem Funktionsumfang entwickelt werden. Dazu zählen (...)

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Betriebssystem (BS)

GHS-INTEGRITY-RTOS — Green Hills INTEGRITY RTOS

The flagship of Green Hills Software operating systems—the INTEGRITY RTOS—is built around a partitioning architecture to provide embedded systems with total reliability, absolute security, and maximum real-time performance. With its leadership pedigree underscored by certifications in a (...)
Unterstützte Produkte und Hardware
Support-Software

VCTR-3P-MICROSAR — Vector MICROSAR AUTOSAR-Software für Mikrocontroller und Hochleistungscomputer (HPCs)

Die MICROSAR- und DaVinci-Produktfamilien vereinfachen die Steuergeräte-Entwicklung mit ausgefeilter Embedded-Software und leistungsstarken Entwicklungswerkzeugen für Mikrocontroller und HPCs. Mit fortschrittlicher Infrastruktursoftware schaffen Sie eine optimale Basis für Ihre Steuergeräte und (...)

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Simulationsmodell

DRA7xxP and TDA2Px BSDL Files

SPRM750.ZIP (34 KB) - BSDL-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

DRA7xxP and TDA2Px IBIS Files

SPRM748.ZIP (36622 KB) - IBIS-Modell
Unterstützte Produkte und Hardware
Simulationsmodell

DRA7xxP and TDA2Px Thermal Model

SPRM749.ZIP (2 KB) - Wärmemodell
Unterstützte Produkte und Hardware
Berechnungstool

CLOCKTREETOOL — Taktbaum-Tool für Sitara, Automobilanwendungen, Sichtanalytik und digitale Signalprozessoren

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:

  • Visualize the device clock tree
  • Interact with clock tree (...)
Unterstützte Produkte und Hardware
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
FCCSP (ABZ) 760 Ultra Librarian

Bestellen & Qualität

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