DS90CR287

AKTIV

28-Bit Channel-Link-LVDS-Sender, +3,3V Rising Edge Data Strobe – 85 MHz

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Datenblatt

document-pdfAcrobat DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G) (Englisch)

DS90CR287

AKTIV

Datenblatt

Jetzt bestellen

Produktdetails

Protocols

Catalog

Device type

Transmitter

Rating

Catalog

Operating temperature range (°C)

-10 to 70

Protocols

Catalog

Device type

Transmitter

Rating

Catalog

Operating temperature range (°C)

-10 to 70

TSSOP (DGG)

56

113.4 mm² (14 mm × 8.1 mm)

NFBGA (NZC)

64

64 mm² (8 mm × 8 mm)

20 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
2.5 / 0 ns Set & Hold Times on TxINPUTs
Low Power Consumption
±1V Common-Mode Range (around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 2.38 Gbps Throughput
Up to 297.5 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead TSSOP Package

20 to 85 MHz Shift Clock Support
50% Duty Cycle on Receiver Output Clock
2.5 / 0 ns Set & Hold Times on TxINPUTs
Low Power Consumption
±1V Common-Mode Range (around +1.2V)
Narrow Bus Reduces Cable Size and Cost
Up to 2.38 Gbps Throughput
Up to 297.5 Mbytes/sec Bandwidth
345 mV (typ) Swing LVDS Devices for Low EMI
PLL Requires no External Components
Rising Edge Data Strobe
Compatible with TIA/EIA-644 LVDS Standard
Low Profile 56-Lead TSSOP Package

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

The DS90CR287 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted.

The DS90CR288A receiver converts the four LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 85 MHz, 28 bits of TTL data are transmitted at a rate of 595 Mbps per LVDS data channel. Using a 85 MHz clock, the data throughput is 2.38 Gbit/s (297.5 Mbytes/sec).

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces.

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Technische Dokumentation

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Top-Dokumentation	Typ	Titel	Format-Optionen	Datum
*	Datenblatt	DS90CR287/DS90CR288A 3.3V Rising Edge Data Strobe LVDS 28-Bit Channel Link 85MHz datasheet (Rev. G)		05.03.2013
	Anwendungshinweis	High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs		09.11.2018
	Anwendungshinweis	Receiver Skew Margin for Channel Link I and FPD Link I Devices	PDF \| HTML	13.01.2016
	Anwendungshinweis	Improving the Robustness of Channel Link Designs with Channel Link II Ser/Des (Rev. A)		26.04.2013
	Designleitfaden	Channel Link I Design Guide		29.03.2007
	Anwendungshinweis	Multi-Drop Channel-Link Operation		04.10.2004
	Anwendungshinweis	CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications		05.10.1998

Design und Entwicklung

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Evaluierungsplatine

FLINK3V8BT-85 — Evaluierungskit für FPD-Link-Familie von Serializer- und Deserializer-LVDS-Bausteinen

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

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