Startseite Schnittstelle LVDS-, M-LVDS- und PECL-ICs
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LVDS-, M-LVDS- und PECL-ICs

DS92LV18

AKTIV

18-Bit-Bus-LVDS-Serializer/Deserializer – 15–66 MHz

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Datenblatt

DS92LV18

AKTIV
Datenblatt Jetzt bestellen

Produktdetails

Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2376 Input signal BLVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
Function SerDes Protocols Channel-Link I Number of transmitters 1 Number of receivers 1 Supply voltage (V) 3.3 Signaling rate (MBits) 2376 Input signal BLVDS, LVTTL Output signal BLVDS, LVDS, LVTTL Rating Catalog Operating temperature range (°C) -40 to 85
LQFP (PN) 80 196 mm² 14 x 14
  • 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
  • ±100 mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.0kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

  • 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376 Gbps Full Duplex Throughput)
  • Independent Transmitter and Receiver Operation with Separate Clock, Enable, and Power Down Pins
  • Hot Plug Protection (Power Up High Impedance) and Synchronization (Receiver Locks to Random Data)
  • Wide ±5% Reference Clock Frequency Tolerance for Easy System Design Using Locally-Generated Clocks
  • Line and Local Loopback Modes
  • Robust BLVDS Serial Transmission Across Backplanes and Cables for Low EMI
  • No External Coding Required
  • Internal PLL, No External PLL Components Required
  • Single +3.3V Power Supply
  • Low Power: 90mA (typ) Transmitter, 100mA (typ) at 66 MHz with PRBS-15 Pattern
  • ±100 mV Receiver Input Threshold
  • Loss of Lock Detection and Reporting Pin
  • Industrial −40 to +85°C Temperature Range
  • >2.0kV HBM ESD
  • Compact, Standard 80-Pin LQFP Package

All trademarks are the property of their respective owners.

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.

The DS92LV18 Serializer/Deserializer (SERDES) pair transparently translates a 18–bit parallel bus into a BLVDS serial stream with embedded clock information. This single serial stream simplifies transferring a 18-bit, or less, bus over PCB traces and cables by eliminating the skew problems between parallel data and clock paths. It saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.

This SERDES pair includes built-in system and device test capability. The line loopback feature enables the user to check the integrity of the serial data transmission paths of the transmitter and receiver while deserializing the serial data to parallel data at the receiver outputs. The local loopback feature enables the user to check the integrity of the transceiver from the local parallel-bus side.

The DS92LV18 incorporates modified BLVDS signaling on the high-speed I/O. BLVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. The equal and opposite currents through the differential data path control EMI by coupling the resulting fringing fields together.
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Technische Dokumentation

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Typ Titel Datum
* Data sheet DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz datasheet (Rev. E) 18 Apr 2013
Application note DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) 29 Apr 2013
Application note External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A) 26 Apr 2013
User guide 18-Bit SerDes Evaluation Kit User Manual 25 Jan 2012
Design guide 18-bit SerDes Design Guide (DS92LV18, SCAN921821) 29 Mär 2007

Design und Entwicklung

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Evaluierungsplatine

LVDS-18B-EVK — Evaluierungsplatine für LVDS-SerDes mit 18-Bit-Bus (15 bis 66 MHz)

The LVDS-18B-EVK evaluation kit (EVK) is a complete kit to evaluate our 18-bit SerDes devices (DS92LV18 and SCAN921821) with low-cost twisted pair cables and other 100-Ω differential cables.

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