Gehäuseinformationen
| Gehäuse | Pins TQFP (PAG) | 64 |
| Betriebstemperaturbereich (°C) 0 to 70 |
| Gehäusemenge | Träger 160 | JEDEC TRAY (10+1) |
Merkmale von LMH0031
- SDTV/HDTV Serial Digital Video Standard Compliant
- Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps and 1.485 Gbps Serial Video Data Rates with Auto-Detection
- LSB De-Dithering Option
- Uses Low-Cost 27MHz Crystal or Clock Oscillator Reference
- Fast VCO Lock Time: < 500 µs at 1.485 Gbps
- Built-in Self-Test (BIST) and Video Test Pattern Generator (TPG) Patent Applications Made or Pending
- Automatic EDH/CRC Word and Flag Processing
- Ancillary Data FIFO with Extensive Packet Handling Options
- Adjustable, 4-Deep Parallel Output Video Data FIFO
- Flexible Control and Configuration I/O Port
- LVCMOS Compatible Control Inputs and Clock and Data Outputs
- LVDS and ECL-Compatible, Differential, Serial Inputs
- 3.3V I/O Power Supply and 2.5V Logic Power Supply Operation
- Low Power: Typically 850mW
- 64-Pin TQFP Package
- Commercial Temperature Range 0°C to +70°C
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Beschreibung von LMH0031
The LMH0031 SMPTE 292M / 259M Digital Video Deserializer/Descrambler with Video and Ancillary Data FIFOs is a monolithic integrated circuit that deserializes and decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial component video data, to 20-bit parallel data with a synchronized parallel word-rate clock. It also deserializes and decodes SMPTE 259M, 270Mbps, 360Mbps and SMPTE 344M (proposed) 540Mbps serial component video data, to 10-bit parallel data. Functions performed by the LMH0031 include: clock/data recovery from the serial data, serial-to-parallel data conversion, SMPTE standard data decoding, NRZI-to-NRZ conversion, parallel data clock generation, word framing, CRC and EDH data checking and handling, Ancillary Data extraction and automatic video format determination. The parallel video output features a variable-depth FIFO which can be adjusted to delay the output data up to 4 parallel data clock periods. Ancillary Data may be selectively extracted from the parallel data through the use of masking and control bits in the configuration and control registers and stored in the on-chip FIFO. Reverse LSB dithering is also implemented.
The unique multi-functional I/O port of the LMH0031 provides external access to functions and data stored in the configuration and control registers. This feature allows the designer greater flexibility in tailoring the LMH0031 to the desired application. The LMH0031 is auto-configured to a default operating condition at power-on or after a reset command. Separate power pins for the PLL, deserializer and other functional circuits improve power supply rejection and noise performance.
The LMH0031 has a unique Built-In Self-Test (BIST) and video Test Pattern Generator (TPG). The BIST enables comprehensive testing of the device by the user. The BIST uses the TPG as input data and includes SD and HD component video test patterns, reference black, PLL and EQ pathologicals and a 75% saturation, 8 vertical colour bar pattern, for all implemented rasters. The colour bar pattern has optional transition coding at changes in the chroma and luma bar data. The TPG data is output via the parallel data port.
The LMH0030, SMPTE 292M / 259M Digital Video Serializer with Ancillary Data FIFO and Integrated Cable Driver, is the ideal complement to the LMH0031.
The LMH0031's internal circuitry is powered from +2.5 Volts and the I/O circuitry from a +3.3 Volt supply. Power dissipation is typically 850mW. The device is packaged in a 64-pin TQFP.