Gehäuseinformationen
| Gehäuse | Pins WQFN (RLJ) | 38 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 3.000 | LARGE T&R |
Merkmale von SN65DP141
- Supports VESA DisplayPort 1.4a, 2.0, and eDP 1.4
- Quad channel linear redriver supporting data rates up to 12 Gbps including DisplayPort RBR, HBR, HBR2, HBR3, and UHBR10
- Protocol agnostic
- Transparent to DP link training
- Position independent on the link suitable for source, sink, and cable applications
- 15-dB analog equalization at 6 GHz
- Output linear dynamic range: 1200 mV
- Bandwidth: >20 GHz
- Better than 16-dB return loss at 6 GHz
- 2.5-V or 3.3-V ±5% single power supply option
- Low power consumption with 80 mW per channel at 2.5 V VCC
- GPIO or I2C control
Beschreibung von SN65DP141
The SN65DP141 is an asynchronous, protocol-agnostic, low latency, four-channel linear equalizer optimized for use up to 12 Gbps and compensates for losses due to board traces and cables.
The device is transparent to DisplayPort (DP) link training such a way that a DP source and a sink can perform effective link training overcoming traditional aux snooping re-drivers’ shortcomings. Additionally, the device is position independent. It can be placed inside source, cable or sink effectively providing a negative loss component to the overall link budget. Linear equalization inside SN65DP141 also increases link margin when used with a receiver implementing Decision Feedback Equalization (DFE).
SN65DP141 allows independent channel control for equalization, gain, dynamic range using both I2C and GPIO configurations.
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