Gehäuseinformationen
| Gehäuse | Pins PDIP (P) | 8 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 50 | TUBE |
Merkmale von SN65HVD05
- Minimum differential output voltage of 2.5 V Into a 54-Ω load
- Open-circuit, short-circuit, and idle-bus failsafe receiver
- 1/8th Unit-load option available (Up to 256 nodes on the bus)
- Bus-pin ESD protection exceeds 16 kV HBM
- Driver output slew rate control options
- Electrically compatible with ANSI TIA/EIA-485-A standard
- Low-current standby mode: 1 µA typical
- Glitch-free power-up and power-down protection for hot-plugging applications
- Pin compatible with industry standard SN75176
Beschreibung von SN65HVD05
The SN65HVD05, SN75HVD05, SN65HVD06, SN75HVD06, SN65HVD07, and SN75HVD07 combine a 3-state differential line driver and differential line receiver. They are designed for balanced data transmission and interoperate with ANSI TIA/EIA-485-A and ISO 8482E standard-compliant devices. The driver is designed to provide a differential output voltage greater than that required by these standards for increased noise margin. The drivers and receivers have active-high and active-low enables respectively, which can be externally connected together to function as direction control.
The driver differential outputs and receiver differential inputs connect internally to form a differential input/ output (I/O) bus port that is designed to offer minimum loading to the bus whenever the driver is disabled or not powered. These devices feature wide positive and negative common-mode voltage ranges, making them suitable for party-line applications.