Gehäuseinformationen
| Gehäuse | Pins TSSOP (PW) | 16 |
| Betriebstemperaturbereich (°C) -40 to 85 |
| Gehäusemenge | Träger 90 | TUBE |
Merkmale von SN65LVDM22
- Meets or Exceeds the Requirements of ANSI TIA/EIA-644-1995 Standard
- Designed for Clock Rates up to 200 MHz (400 Mbps)
- Designed for Data Rates up to 250 Mbps
- Pin Compatible With SN65LVDS122 and SN65LVDT122, 1.5 Gbps 2x2 Crosspoint Switch From TI
- ESD Protection Exceeds 12 kV on Bus Pins
- Operates From a Single 3.3-V Supply
- Low-Voltage Differential Signaling With Output Voltages of 350 mV Into:
- 100-
Load (SN65LVDS22) - 50- Load (SN65LVDM22)
- 100-
- Propagation Delay Time; 4 ns Typ
- Power Dissipation at 400 Mbps of 150 mW
- Bus Pins Are High Impedance When Disabled or With VCC Less Than 1.5 V
- LVTTL Levels Are 5 V Tolerant
- Open-Circuit Fail Safe Receiver
Beschreibung von SN65LVDM22
The SN65LVDS22 and SN65LVDM22 are differential line drivers and receivers that use low-voltage differential signaling (LVDS) to achieve signaling rates as high as 400 Mbps. The receiver outputs can be switched to either or both drivers through the multiplexer control signals S0 and S1. This allows the flexibility to perform splitter or signal routing functions with a single device.
The TIA/EIA-644 standard compliant electrical interface provides a minimum differential output voltage magnitude of 247 mV into a 100- load.
The intended application of these devices and signaling technique is for both point-to-point baseband (single termination) and multipoint (double termination) data transmissions over controlled impedance media. The transmission media may be printed-circuit board traces, backplanes, or cables. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other application specific characteristics).
The SN65LVDS22 and SN65LVDM22 are characterized for operation from –40°C to 85°C.