Produktdetails

Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
Supply voltage (min) (V) 4.5 Supply voltage (max) (V) 5.5 Number of channels 8 IOL (max) (mA) 64 IOH (max) (mA) -32 Input type TTL-Compatible CMOS Output type 3-State Features Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family ABT Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 28 184.37 mm² 17.9 x 10.3 SSOP (DL) 28 98.6355 mm² 9.53 x 10.35
  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Functionally Equivalent to 'F652 and 'ABT652 in the Normal-Function Mode
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells Per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

 

SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.

  • Members of the Texas Instruments SCOPETM Family of Testability Products
  • Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
  • Functionally Equivalent to 'F652 and 'ABT652 in the Normal-Function Mode
  • SCOPETM Instruction Set
    • IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ
    • Parallel-Signature Analysis at Inputs With Masking Option
    • Pseudo-Random Pattern Generation From Outputs
    • Sample Inputs/Toggle Outputs
    • Binary Count From Outputs
    • Even-Parity Opcodes
  • Two Boundary-Scan Cells Per I/O for Greater Flexibility
  • State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
  • Package Options Include Shrink Small-Outline (DL) and Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Ceramic DIPs (JT)

 

SCOPE and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT8652 scan test devices with octal bus transceivers and registers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F652 and 'ABT652 octal bus transceivers and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers and registers.

 

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and inputs. Since the input is active low, the A outputs are active when is low and are in the high-impedance state when is high. Figure 1 shows the four fundamental bus-management functions that can be performed with the 'ABT8652.

In the test mode, the normal operation of the SCOPETM bus transceivers and registers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8652 is characterized for operation from -40°C to 85°C.

 

 

 

The 'ABT8652 scan test devices with octal bus transceivers and registers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are functionally equivalent to the 'F652 and 'ABT652 octal bus transceivers and registers. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in normal mode does not affect the functional operation of the SCOPETM octal bus transceivers and registers.

 

Data flow in each direction is controlled by clock (CLKAB and CLKBA), select (SAB and SBA), and output-enable (OEAB and ) inputs. For A-to-B data flow, data on the A bus is clocked into the associated registers on the low-to-high transition of CLKAB. When SAB is low, real-time A data is selected for presentation to the B bus (transparent mode). When SAB is high, stored A data is selected for presentation to the B bus (registered mode). When OEAB is high, the B outputs are active. When OEAB is low, the B outputs are in the high-impedance state. Control for B-to-A data flow is similar to that for A-to-B data flow but uses CLKBA, SBA, and inputs. Since the input is active low, the A outputs are active when is low and are in the high-impedance state when is high. Figure 1 shows the four fundamental bus-management functions that can be performed with the 'ABT8652.

In the test mode, the normal operation of the SCOPETM bus transceivers and registers is inhibited and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations as described in IEEE Standard 1149.1-1990.

Four dedicated test pins control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT8652 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT8652 is characterized for operation from -40°C to 85°C.

 

 

 

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Technische Dokumentation

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Typ Titel Datum
* Data sheet Scan Test Devices With Octal Bus Transceivers And Registers datasheet (Rev. F) 01 Dez 1996
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
EVM User's guide LASP Demo Board User's Guide 01 Nov 2005
Application note Programming CPLDs Via the 'LVT8986 LASP 01 Nov 2005
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Quad Flatpack No-Lead Logic Packages (Rev. D) 16 Feb 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 Mai 2002
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A) 01 Mär 1997
Application note Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A) 01 Dez 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 Okt 1996
Application note Live Insertion 01 Okt 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 Mai 1996

Design und Entwicklung

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Simulationsmodell

BSDL Model of SN74ABT8652

SCTM009.ZIP (2 KB) - BSDL Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
SOIC (DW) 28 Ultra Librarian
SSOP (DL) 28 Ultra Librarian

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