Produktdetails

Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Technology family AHC Rating Catalog Operating temperature range (°C) -40 to 125
Supply voltage (min) (V) 2 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 8 IOH (max) (mA) -8 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Very high speed (tpd 5-10ns) Technology family AHC Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Operating range 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low power consumption, 10-µA max ICC
  • ±8-mA output drive at 5 V
  • Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
  • Latch-up performance exceeds 250 mA per JESD 17
  • Operating range 2 V to 5.5 V
  • Max tpd of 6.5 ns at 5 V
  • Low power consumption, 10-µA max ICC
  • ±8-mA output drive at 5 V
  • Schmitt-trigger action at all inputs makes the circuit tolerant for slower input rise and fall time
  • Latch-up performance exceeds 250 mA per JESD 17

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

The SN74AHC1G04 contains one inverter gate. The device performs the Boolean function Y = A.

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SN74LVC1G04 AKTIV Einzelner 1,65-V- bis 5,5-V-Inverter Shorter average propagation delay (5.5ns), higher average drive strength (24mA)

Technische Dokumentation

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Typ Titel Datum
* Data sheet SN74AHC1G04 Single Inverter Gate datasheet (Rev. V) PDF | HTML 01 Feb 2024
Product overview Configurable Timed Reset Using Discrete Logic (Rev. A) PDF | HTML 02 Mai 2023
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note How to Select Little Logic (Rev. A) 26 Jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
Application note Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) 02 Dez 2002
Application note Texas Instruments Little Logic Application Report 01 Nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Design guide AHC/AHCT Designer's Guide February 2000 (Rev. D) 24 Feb 2000
Application note Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) 08 Sep 1999
Product overview Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) 01 Apr 1998
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dez 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Live Insertion 01 Okt 1996

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Evaluierungsplatine

5-8-LOGIC-EVM — Generisches Logik-Evaluierungsmodul für 5- bis 8-polige DCK-, DCT-, DCU-, DRL- und DBV-Gehäuse

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Benutzerhandbuch: PDF
Simulationsmodell

SN74AHC1G04 Behavioral SPICE Model

SCLM274.ZIP (7 KB) - PSpice Model
Simulationsmodell

SN74AHC1G04 IBIS Model

SCLM003.ZIP (13 KB) - IBIS Model
Simulationsmodell

SN74AHC1G04 TINA-TI Reference Design

SCLM113.TSC (25 KB) - TINA-TI Reference Design
Simulationsmodell

SN74AHC1G04 TINA-TI Spice Model

SCLM114.ZIP (3 KB) - TINA-TI Spice Model
Simulationsmodell

SN74AHC1G04H IBIS Model

SCLM028.ZIP (6 KB) - IBIS Model
Simulationsmodell

SN74AHC1G04H IBIS Model

SCLM029.ZIP (5 KB) - IBIS Model
Simulationsmodell

SN74AHC1G04H IBIS Model

SCLM030.ZIP (6 KB) - IBIS Model
Simulationsmodell

SN74AHC1G04H IBIS Model

SCLM031.ZIP (5 KB) - IBIS Model
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Design guide: PDF
Schaltplan: PDF
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Schaltplan: PDF
Referenzdesigns

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TIDA-01037 is a 20-bit, 1 MSPS isolated analog input data acquisition reference design that utilizes two different isolator devices to maximize signal chain SNR and sample rate performance. For signals requiring low jitter, such as ADC sampling clocks, TI’s ISO73xx family of low jitter (...)
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Schaltplan: PDF
Referenzdesigns

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Referenzdesigns

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Referenzdesigns

TIDA-01052 — ADC-Treiber-Referenzdesign zur Verbesserung des Full Scale THD bei negativer Versorgung

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Design guide: PDF
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Gehäuse Pins Herunterladen
SOT-23 (DBV) 5 Optionen anzeigen
SOT-5X3 (DRL) 5 Optionen anzeigen
SOT-SC70 (DCK) 5 Optionen anzeigen

Bestellen & Qualität

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  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
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  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
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  • Werksstandort
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