SN74GTLPH16912

AKTIV

18-Bit-LVTTL-zu-GTLP-Universal-Bustransceiver

Produktdetails

Technology family GTLP Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
Technology family GTLP Applications GTL Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 56 113.4 mm² 14 x 8.1
  • Member of Texas Instruments' Widebus™ Family
  • UBT™ Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and Clock-Enabled Modes
  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • LVTTL Interfaces Are 5-V Tolerant
  • Medium-Drive GTLP Outputs (50 mA)
  • LVTTL Outputs (\x9624 mA/24 mA)
  • GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Bus Hold on A-Port Data Inputs
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.

  • Member of Texas Instruments' Widebus™ Family
  • UBT™ Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, and Clock-Enabled Modes
  • TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
  • OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
  • Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
  • LVTTL Interfaces Are 5-V Tolerant
  • Medium-Drive GTLP Outputs (50 mA)
  • LVTTL Outputs (\x9624 mA/24 mA)
  • GTLP Rise and Fall Times Designed for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
  • Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
  • Bus Hold on A-Port Data Inputs
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

OEC, TI, TI-OPC, UBT, and Widebus are trademarks of Texas Instruments.

The SN74GTLPH16912 is a medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 .

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74GTLPH16912 is a medium-drive, 18-bit UBT™ transceiver that provides LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation. It allows for transparent, latched, clocked, and clock-enabled modes of data transfer. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels. High-speed (about three times faster than standard TTL or LVTTL) backplane operation is a direct result of GTLP's reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuits minimize bus-settling time and have been designed and tested using several backplane models. The medium drive allows incident-wave switching in heavily loaded backplanes with equivalent load impedance down to 19 .

GTLP is the Texas Instruments (TI™) derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLPH16912 is given only at the preferred higher noise-margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL and 5-V CMOS inputs. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff, power-up 3-state, and BIAS VCC. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

Active bus-hold circuitry holds unused or undriven LVTTL data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Herunterladen Video mit Transkript ansehen Video

Technische Dokumentation

star =Von TI ausgewählte Top-Empfehlungen für dieses Produkt
Keine Ergebnisse gefunden. Bitte geben Sie einen anderen Begriff ein und versuchen Sie es erneut.
Alle anzeigen 17
Typ Titel Datum
* Data sheet 18-Bit LVTTL-to-GTLP Universal Bus Transceiver datasheet (Rev. C) 26 Jul 2001
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dez 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 Mai 2002
Application note Logic in Live-Insertion Applications With a Focus on GTLP 14 Jan 2002
User guide GTLP/GTL Logic High-Performance Backplane Drivers Data Book (Rev. A) 15 Sep 2001
Application note Achieving Maximum Speed on Parallel Buses With Gunning Transceiver Logic (GTLP) 05 Apr 2001
Selection guide Advanced Bus Interface Logic Selection Guide 09 Jan 2001
Application brief Texas Instruments GTLP Frequently Asked Questions 01 Jan 2001
Application note Fast GTLP Backplanes With the GTLPH1655 (Rev. A) 19 Sep 2000
More literature High Level Brochure of Gunning Transceiver Logic Plus 14 Jan 2000

Design und Entwicklung

Weitere Bedingungen oder erforderliche Ressourcen enthält gegebenenfalls die Detailseite, die Sie durch Klicken auf einen der unten stehenden Titel erreichen.

Simulationsmodell

H-SPICE Model of SN74GTLPH16912 (Rev. A)

SCEJ156A.ZIP (107 KB) - HSpice Model
Simulationsmodell

SN74GTLPH16912 IBIS Model

SCEM201.ZIP (28 KB) - IBIS Model
Gehäuse Pins CAD-Symbole, Footprints und 3D-Modelle
TSSOP (DGG) 56 Ultra Librarian

Bestellen & Qualität

Beinhaltete Information:
  • RoHS
  • REACH
  • Bausteinkennzeichnung
  • Blei-Finish/Ball-Material
  • MSL-Rating / Spitzenrückfluss
  • MTBF-/FIT-Schätzungen
  • Materialinhalt
  • Qualifikationszusammenfassung
  • Kontinuierliches Zuverlässigkeitsmonitoring
Beinhaltete Information:
  • Werksstandort
  • Montagestandort

Support und Schulungen

TI E2E™-Foren mit technischem Support von TI-Ingenieuren

Inhalte werden ohne Gewähr von TI und der Community bereitgestellt. Sie stellen keine Spezifikationen von TI dar. Siehe Nutzungsbedingungen.

Bei Fragen zu den Themen Qualität, Gehäuse oder Bestellung von TI-Produkten siehe TI-Support. ​​​​​​​​​​​​​​

Videos