These 8-bit addressable latches are designed for general purpose storage
applications in digital systems. Specific uses include working registers,
serial-holding registers, and active-high decoders or demultiplexers. They
are multifunctional devices capable of storing single-line data in eight addressable
latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear
(CLR\) and enable (G\) inputs as enumerated in the function
table. In the addressable-latch mode, data at the data-in terminal is written
into the addressed latch. The addressed latch will follow the data input with
all unaddressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous states and are unaffected by the
data or address inputs. To eliminate the possibility of entering erroneous
data in the latches, enable G\ should be held high (inactive) while
the address lines are changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the D input with all other outputs
low. In the clear mode, all outputs are low and unaffected by the address
and data inputs.
The SN54259 and SN54LS259B are characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74259 and SN74LS259B
are characterized for operation from 0°C to 70°C.
These 8-bit addressable latches are designed for general purpose storage
applications in digital systems. Specific uses include working registers,
serial-holding registers, and active-high decoders or demultiplexers. They
are multifunctional devices capable of storing single-line data in eight addressable
latches, and being a 1-of-8 decoder or demultiplexer with active-high outputs.
Four distinct modes of operation are selectable by controlling the clear
(CLR\) and enable (G\) inputs as enumerated in the function
table. In the addressable-latch mode, data at the data-in terminal is written
into the addressed latch. The addressed latch will follow the data input with
all unaddressed latches remaining in their previous states. In the memory
mode, all latches remain in their previous states and are unaffected by the
data or address inputs. To eliminate the possibility of entering erroneous
data in the latches, enable G\ should be held high (inactive) while
the address lines are changing. In the 1-of-8 decoding or demultiplexing mode,
the addressed output will follow the level of the D input with all other outputs
low. In the clear mode, all outputs are low and unaffected by the address
and data inputs.
The SN54259 and SN54LS259B are characterized for operation over the full
military temperature range of -55°C to 125°C. The SN74259 and SN74LS259B
are characterized for operation from 0°C to 70°C.