NUEVO

ADC3668

ACTIVO

ADC de 16 bits, 2 canales y 250 MSPS con interfaz LVDS y decimación de hasta 32768x

Haga su pedido ahora

Hoja de datos

document-pdfAcrobat ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B) (Inglés) PDF | HTML

ADC3668

ACTIVO

Hoja de datos

Haga su pedido ahora

Detalles del producto

Sample rate (max) (Msps)

250

Resolution (Bits)

16

Number of input channels

2

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

640

Architecture

Pipeline

SNR (dB)

75.5

ENOB (Bits)

12.3

SFDR (dB)

79

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

Sample rate (max) (Msps)

250

Resolution (Bits)

16

Number of input channels

2

Interface type

DDR LVDS

Analog input BW (MHz)

1400

Features

Decimating Filter, Differential Inputs, High Dynamic Range, High Performance, Input buffer, Low latency, Low power

Rating

Catalog

Peak-to-peak input voltage range (V)

2

Power consumption (typ) (mW)

640

Architecture

Pipeline

SNR (dB)

75.5

ENOB (Bits)

12.3

SFDR (dB)

79

Operating temperature range (°C)

-40 to 85

Input buffer

Yes

VQFNP (RTD)

64

81 mm² 9 x 9

16-bit, dual channel 250 and 500MSPS ADC
Noise spectral density: -160.4dBFS/Hz
Thermal Noise: 76.4dBFS
Single core (non-interleaved) ADC architecture
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100Ω and 200Ω termination
Input fullscale: 2VPP
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 75.6dBFS
- SFDR HD2,3: 80dBc
- SFDR worst spur: 94dBFS
INL: ±2 LSB (typical)
DNL: ±0.5 LSB (typical)
Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
DDR/Serial LVDS interface
- 16-bit Parallel DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation
Power consumption: 300mW/channel (500MSPS)

16-bit, dual channel 250 and 500MSPS ADC
Noise spectral density: -160.4dBFS/Hz
Thermal Noise: 76.4dBFS
Single core (non-interleaved) ADC architecture
Aperture jitter: 75fs
Buffered analog inputs
- Programmable 100Ω and 200Ω termination
Input fullscale: 2VPP
Full power input bandwidth (-3dB): 1.4GHz
Spectral performance (fIN = 70MHz, -1dBFS):
- SNR: 75.6dBFS
- SFDR HD2,3: 80dBc
- SFDR worst spur: 94dBFS
INL: ±2 LSB (typical)
DNL: ±0.5 LSB (typical)
Digital down-converters (DDCs)
- Up to four independent DDCs
- Complex and real decimation
- Decimation: /2, /4 to /32768 decimation
- 48-bit NCO phase coherent frequency hopping
DDR/Serial LVDS interface
- 16-bit Parallel DDR LVDS for DDC bypass
- Serial LVDS for decimation
- 32-bit output option for high decimation
Power consumption: 300mW/channel (500MSPS)

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

The ADC3668 and ADC3669 (ADC366x) are a 16-bit, 250MSPS and 500MSPS, dual channel analog to digital converters (ADC). The devices are designed for high signal-to-noise ratio (SNR) and deliver a noise spectral density of −160dBFS/Hz (500MSPS).

The ADC366x includes an optional quad band digital down-converter (DDC) supporting wide band decimation by 2 to narrow band decimation by 32768. The DDC uses a 48-bit NCO which supports phase coherent and phase continuous frequency hopping.

The ADC366x is outfitted with a flexible LVDS interface. In decimation bypass mode, the device uses a 16-bit wide parallel DDR LVDS interface. When using decimation, the output data is transmitted using a serial LVDS interface reducing the number of lanes needed as decimation increases. For high decimation ratios, the output resolution can be increased to 32-bit.

The power efficient ADC architecture consumes 300mW/ch at 500MSPS and provides power scaling with lower sampling rates (250mW/ch at 250MSPS).

filter

Buscar otro/a ADC de alta velocidad (≥ 10 MSPS)

Descargar Ver vídeo con transcripción Video

Documentación técnica

star

=Principal documentación para este producto seleccionada por TI

No se encontraron resultados. Borre su búsqueda y vuelva a intentarlo.

Ver todo 5

	Tipo	Título		Fecha
*	Data sheet	ADC3668, ADC3669 Dual-Channel, 16-Bit 250MSPS and 500MSPS Analog-to-Digital Converter (ADC) datasheet (Rev. B)	PDF \| HTML	05 jun 2025
	Analog Design Journal	Sampling around Nyquist holes in high-speed converters	PDF \| HTML	16 may 2025
	Application note	Comparing Active vs. Passive High-Speed/RF A/D Converter Front Ends	PDF \| HTML	28 mar 2025
	Application note	Evaluating High-Speed, RF ADC Converter Front-end Architectures	PDF \| HTML	26 mar 2025
	Application note	Improving MSPS ADC’s SFDR While Relaxing AAF Requirements and Using Integrated DDC Features	PDF \| HTML	18 feb 2025

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

ADC3669EVM — Módulo de evaluación ADC3669 (acoplado a CC)

El módulo de evaluación (EVM) ADC3669EVM-DC está diseñado para evaluar la familia ADC3669 de convertidores analógico a digital (ADC) de alta velocidad con un circuito frontal acoplado a la CC. El ADC3669EVM-DC está equipado con un ADC3669. El ADC3669 es un ADC de 16 bits de doble canal con una (...)

Guía del usuario: PDF | HTML

View Options

Herramienta de simulación

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

PSpice® para TI es un entorno de diseño y simulación que ayuda a evaluar la funcionalidad de los circuitos analógicos. Esta completa suite de diseño y simulación utiliza un motor de análisis analógico de Cadence®. Disponible sin ningún costo, PSpice para TI incluye una de las bibliotecas de modelos (...)

Solicitar

Encapsulado	Pines	Símbolos CAD, huellas y modelos 3D
VQFNP (RTD)	64	Ultra Librarian

Se aplican los Términos y condiciones estándar de TI para los elementos de evaluación.

ADC3668

ADC de 16 bits, 2 canales y 250 MSPS con interfaz LVDS y decimación de hasta 32768x

ADC3668

Detalles del producto

Documentación técnica

Diseño y desarrollo

ADC3669EVM — Módulo de evaluación ADC3669 (acoplado a CC)

PSPICE-FOR-TI — PSpice® para herramienta de diseño y simulación de TI

Pedidos y calidad

Soporte y capacitación

Foros de TI E2E™ con asistencia técnica de los ingenieros de TI

Serie de videos

Videos