The differential LVPECL clock-driver circuit distributes one pair of differential LVPECL clock inputs (CLKIN, CLKIN\) to nine pairs of differential clock (Y, Y\) outputs with minimum skew for clock distribution. It is specifically designed for driving 50-
transmission lines.
When the output-enable (OE\) is low, the nine differential outputs switch at the same frequency as the differential clock inputs. When OE\ is high, the nine differential outputs are in static states (Y outputs are in the low state, Y\ outputs are in the high state).
The VREF output can be strapped to the CLKIN\ input for a single-ended CLKIN input.
The CDC111 is characterized for operation from 0°C to 70°C.
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 1-Line To 9-Line Differential LVPECL Clock Driver datasheet (Rev. G) | 28 ago 1999 | |
| Application note | AC Coupling Between Differential LVPECL, LVDS, HSTL and CML (Rev. C) | 17 oct 2007 | ||
| Application note | DC-Coupling Between Differential LVPECL, LVDS, HSTL, and CML | 19 feb 2003 |
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| Paquete | Pasadores | Descargar |
|---|---|---|
| PLCC (FN) | 28 | Ver opciones |
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