CDCVF2505-Q1
Controlador de reloj PLL para automoción para sincronización, DRAM y aplicaciones de uso general con
CDCVF2505-Q1
- Qualified for Automotive Applications
- Phase-Locked Loop Clock Driver for Synchronous DRAM
and General-Purpose Applications - Spread-Spectrum Clock Compatible
- Operating Frequency: 24 MHz to 200 MHz
- Low Jitter (Cycle-to-Cycle): <150 ps Over the
Range 66 MHz to 200 MHz - Distributes One Clock Input to One Bank of Five Outputs
(CLKOUT Is Used to Tune the Input-Output Delay) - Three-States Outputs When There Is No Input Clock
- Operates From Single 3.3-V Supply
- Available in 8-Pin SOIC Package
- Consumes Less Than 100 µA (Typically) in
Power Down Mode - Internal Feedback Loop Is Used to Synchronize the
Outputs to the Input Clock - 25-
On-Chip Series Damping Resistors - Integrated RC PLL Loop Filter Eliminates the
Need for External Components
The CDCVF2505 is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the output clocks (1Y[0–3] and CLKOUT) to the input clock signal (CLKIN). The CDCVF2505 operates at 3.3 V. It also provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs provides low-skew, low-jitter copies of CLKIN. Output duty cycles are adjusted to 50 percent, independent of duty cycle at CLKIN. The device automatically goes in power-down mode when no input signal is applied to CLKIN.
Unlike many products containing PLLs, the CDCVF2505 does not require an external RC network. The loop filter for the PLLs is included on-chip, minimizing component count, space, and cost.
Because it is based on the PLL circuitry, the CDCVF2505 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization is required following power up and application of a fixed-frequency, fixed-phase signal at CLKIN, and following any changes to the PLL reference.
The CDCVF2505 is characterized for operation from –40°C to 85°C.
Documentación técnica
| Tipo | Título | Fecha | ||
|---|---|---|---|---|
| * | Data sheet | 3.3-V Clock Phase-Locked Loop Clock Driver datasheet | 21 nov 2008 |
Pedidos y calidad
- RoHS
- REACH
- Marcado del dispositivo
- Acabado de plomo/material de la bola
- Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
- Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
- Contenido del material
- Resumen de calificaciones
- Monitoreo continuo de confiabilidad
- Lugar de fabricación
- Lugar de ensamblaje