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Microcontroladores (MCU) y procesadores
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SoC de redes industriales y multimedia

DRA821U

ACTIVO

SoC con Arm® Cortex®-A72 doble, Ethernet de 4 puertos y PCIe de 4 carriles para redes e informáti

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DRA821U

ACTIVO
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Detalles del producto

CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Catalog Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 2 Arm Cortex-A72 Frequency (MHz) 2000 Coprocessors 4 Arm Cortex-R5F Protocols Ethernet, TSN PCIe 1 PCIe Gen 3 Features Networking Operating system FreeRTOS, INTEGRITY, Linux, QNX, SafeRTOS, VxWorks, u-velOSity Security Cryptographic acceleration, Device attestation & anti-counterfeit, Hardware-enforced isolation, Secure boot, Secure debug, Secure storage, Software IP protection Rating Catalog Power supply solution LP8764-Q1, TPS6594-Q1 Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCBGA (ALM) 433 295.84 mm² 17.2 x 17.2

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Processor cores:

  • Dual 64-bit Arm Cortex-A72 microprocessor subsystem at up to 2.0 GHz, 24K DMIPS
    • 1MB L2 shared cache per dual-core Cortex-A72 cluster
    • 32KB L1 DCache and 48KB L1 ICache per A72 core
  • 4× Arm Cortex-R5F MCUs at up to 1.0 GHz with optional lockstep operation, 8K DMIPS
    • 32K I-Cache, 32K D-Cache, 64K L2 TCM
    • 2× Arm Cortex-R5F MCUs in isolated MCU subsystem
    • 2× Arm Cortex-R5F MCUs in general compute partition

    Memory subsystem:

  • 1MB of On-Chip L3 RAM with ECC and coherency
    • ECC error protection
    • Shared coherent cache
    • Supports internal DMA engine
  • External Memory Interface (EMIF) module with ECC
    • Supports LPDDR4 memory types that comply with the JESD209-4B specification. (No support for byte mode LPDDR4 memories, or memories with more than 17 row address bits)
    • Supports speeds up to 3200 MT/s
    • 32-bit and 16-bit data bus with inline ECC bus up to 12.8GB/s
  • General-Purpose Memory Controller (GPMC)
  • 512KB on-chip SRAM in MAIN domain, protected by ECC

    Virtualization:

  • Hypervisor support in Arm Cortex-A72
  • Independent processing subsystems with Arm Cortex-A72, Arm Cortex-R5F with isolated safety MCU island
  • IO virtualization support
    • Peripheral Virtualization Unit (PVU) for low latency high bandwidth peripheral traffic
  • Multi-region firewall support for memory and peripheral isolation
  • Virtualization support with Ethernet, PCIe, and DMA

  • Device security (on select part numbers):

  • Secure boot with secure runtime support
  • Customer programmable root key, up to RSA-4K or ECC-512
  • Embedded hardware security module
  • Crypto hardware accelerators – PKA with ECC, AES, SHA, RNG, DES and 3DES

    Functional Safety:

  • Functional Safety-Compliant targeted (on select part numbers)
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 and IEC 61508 functional safety system design up to ASIL-D/SIL-3 targeted
    • Systematic capability up to ASIL-D/SIL-3 targeted
    • Hardware integrity up to ASIL-D/SIL-3 targeted for MCU Domain
    • Hardware integrity up to ASIL-D/SIL-3 targeted for Extended MCU (EMCU) portion of the Main Domain
    • Hardware integrity up to ASIL-B/SIL-2 targeted for remainder of the Main Domain
    • FFI isolation provided between EMCU and the remainder of the Main Domain
    • Safety-related certification
      • ISO 26262 and IEC 61508 planned
  • AEC-Q100 qualified on part number variants ending in Q1

  • High-speed interfaces:

    • Integrated Ethernet TSN/AVB switch supporting up to 4 (DRA821U4) or 2 (DRA821U2) external ports:
      • One port supports 5Gb, 10Gb USXGMII/XFI
      • All ports support 2.5Gb SGMII
      • All ports support 1Gb SGMII/RGMII
      • DRA821U4: Any single port can support QSGMII (using all 4 internal ports)
      • Non-blocking wire-rate store and forward switch
      • InterVLAN (Layer3) routing support
      • Time synchronization support with IEEE 1588(annex D,E,F)
      • TSN/AVB support for traffic scheduling, shaping
      • Port mirroring feature for debug and diagnostics
      • Policing and rate limiting support
    • One RGMII/RMII port in safety MCU island
  • One PCI-Express Gen3 controller
    • Gen1, Gen2, and Gen3 operation with auto-negotiation
    • 4× lanes
  • One USB 3.1 Gen1 dual-role device subsystem
    • Supports type-C switching
    • Independently configurable as USB host, USB peripheral, or USB dual-role device

    Automotive interfaces:

  • Twenty CAN-FD ports
  • 12× Universal Asynchronous Receiver/Transmitter (UART)
  • 11× Serial Peripheral Interfaces (SPI)
  • One 8-channel ADC
  • 10× Inter-Integrated Circuit ( I2C™)
  • 2× Improved Inter-Integrated Circuit ( I3C)

    Audio interfaces:

  • 3× Multichannel Audio Serial Port (McASP) modules

    Flash memory interfaces:

  • Embedded Multi Media Card ( eMMC™ 5.1) interface
    • Support speeds of up to HS400
  • One Secure Digital 3.0/Secure Digital Input Output 3.0 (SD3.0/SDIO3.0) interfaces
  • One Octal SPI / Xccela™ / HyperBus™ Memory Controller (HBMC) interface
  • 16-nm FinFET technology
  • 17.2 mm x 17.2 mm, 0.8 mm pitch, IPC Class 3 PCB

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).

Jacinto™ DRA821x processors, based on the Armv8 64-bit architecture, are optimized for gateway systems with cloud connectivity. The System-on-Chip (SoC) design reduces system-level costs and complexity through integration—notably, a system MCU, functional safety and security features, and an Ethernet switch for high-speed communication. Integrated diagnostics and functional safety features are targeted to ASIL-D and SIL 3 certification requirements. Real-time control and low-latency communication are enabled by a PCIe controller and a TSN capable Gigabit Ethernet switch.

Up to four general-purpose Arm® Cortex®-R5F subsystems can handle low-level, timing-critical processing tasks and leave the Arm® Cortex®-A72 core unencumbered for advanced and cloud-based applications.

Jacinto DRA821x processors also include the concept of the Extended MCU (eMCU) domain. This domain is a subset of the processors and peripherals on the main domain targeted at higher functional safety enablement, such as ASIL-D/SIL-3. The functional block diagram highlights which IP are included in the eMCU. For more details about eMCU and functional safety, see the DRA821 Safety Manual Processors Texas Instruments Jacinto™ 7 Family of Products (SPRUIX4).
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Fecha
* Data sheet DRA821 Jacinto™ Processors datasheet (Rev. E) PDF | HTML 30 jun 2023
* Errata J7200 DRA821 Silicon Revision 1.0, 2.0 (Rev. E) PDF | HTML 01 dic 2024
* User guide J7200 DRA821 Processor Silicon Revision 1.0 Technical Reference Manual (Rev. D) PDF | HTML 13 dic 2024
Functional safety information J7200, J721E, J721S2, J722S, J742S2, and J784S4 SDL TÜV SÜD Functional Safety Certificate (Rev. A) 25 sep 2025
Application brief Ethernet Firmware Debug Guide PDF | HTML 29 ago 2025
Functional safety information TÜV SÜD Certificate for Functional Safety Software Development Process (Rev. D) 17 jun 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 feb 2025
Application note MCAN Debug Guide PDF | HTML 18 feb 2025
Application note Microcontroller Abstraction Layer on Jacinto™ and Sitara™ Embedded Processors PDF | HTML 28 ene 2025
Application note Jacinto 7 LPDDR4 Board Design and Layout Guidelines (Rev. F) PDF | HTML 05 ago 2024
Application note Jacinto7 AM6x, TDA4x, and DRA8x High-Speed Interface Design Guidelines (Rev. A) PDF | HTML 04 jun 2024
Application note MMC SW Tuning Algorithm (Rev. A) PDF | HTML 14 may 2024
Application note Jacinto7 AM6x/TDA4x/DRA8x Schematic Checklist (Rev. B) PDF | HTML 04 abr 2024
Application note Jacinto7 HS Device Customer Return Process PDF | HTML 16 nov 2023
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 nov 2023
Application note Jacinto7 DDRSS Register Configuration Tool (Rev. B) PDF | HTML 30 ene 2023
Application note UART Log Debug System on Jacinto 7 SoC PDF | HTML 09 ene 2023
Functional safety information Jacinto Functional Safety Enablers (Rev. A) PDF | HTML 12 dic 2022
User guide Powering DRA821 with TPS6594-Q1 and LP8764-Q1 (Rev. A) PDF | HTML 12 sep 2022
Application note How to Linux Fast Boot on DRA821U (Rev. A) PDF | HTML 28 jul 2022
Application note Dual-TDA4x System Solution PDF | HTML 29 abr 2022
Application note SPI Enablement & Validation on TDA4 Family PDF | HTML 05 abr 2022
Application note Enabling MAC2MAC Feature on Jacinto7 Soc 10 ene 2022
More literature Jacinto™ 7 automotive processors 14 dic 2021
Application note Jacinto 7 Thermal Management Guide - Software Strategies PDF | HTML 10 dic 2021
User guide Single PMIC User's Guide for Jacinto 7 DRA821, PDN-2A PDF | HTML 09 nov 2021
Functional safety information Leverage Jacinto 7 Processors Functional Safety Features for Automotive Designs (Rev. A) PDF | HTML 13 oct 2021
Application note TISCI Server Integration in Vector AUTOSAR PDF | HTML 16 jul 2021
Application note TDA4 Flashing Techniques PDF | HTML 08 jul 2021
Application note J721E DDR Firewall Example PDF | HTML 01 jul 2021
Functional safety information Build safer, efficient, intelligent and autonomous robots 04 mar 2021
White paper Security Enablers on Jacinto™ 7 Processors 04 ene 2021
Technical article Tailor-made gateway processors lay the groundwork for zone architectures PDF | HTML 17 nov 2020
White paper Enabling Differentiation through MCU Integration on Jacinto™ 7 Processors 22 oct 2020
White paper Evolving automotive gateways for next-generation vehicles (Rev. B) 09 oct 2020
Application note OSPI Tuning Procedure PDF | HTML 08 jul 2020

Diseño y desarrollo

Soluciones de alimentación

Busque las soluciones de alimentación disponibles para el DRA821U. TI ofrece soluciones de alimentación para sistemas en chip (SoC), procesadores, microcontroladores, sensores y matrices de compuertas programables de campo (FPGA), sean o no de TI.

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Placa de evaluación

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Guía del usuario: PDF | HTML
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Placa de evaluación

J7EXPCXEVM — Tarjeta de expansión de conmutador Gateway/Ethernet

Expand the capabilities of the J721EXCP01EVM common processor board for evaluating Jacinto 7 processors in vision analytics and networking applications in automotive and industrial markets with our Gateway/Ethernet switch expansion card.

Guía del usuario: PDF | HTML
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Sonda de depuración

TMDSEMU560V2STM-U — Sonda de depuración USB de seguimiento del sistema XDS560v2

The XDS560v2 is the highest performance of the XDS560™ family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).  Note that it does not support serial wire debug (SWD).

All XDS debug probes support Core and System Trace in all ARM and DSP processors (...)

No disponible en TI.com
Sonda de depuración

LB-3P-TRACE32-ARM — Sistema de depuración y seguimiento Lauterbach TRACE32 para microcontroladores y procesadores basado

Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of Arm®-based microcontrollers and processors. The globally renowned debug and trace solutions for embedded systems and SoCs are the perfect (...)

Desde: Lauterbach GmbH
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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-J7200 — Linux SDK for DRA821 Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-LINUX-RT-J7200 — Linux-RT SDK for DRA821 Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-QNX-J7200 — QNX SDK for DRA821 Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)

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Kit de desarrollo de software (SDK)

PROCESSOR-SDK-RTOS-J7200 — RTOS SDK for DRA821 Jacinto™ Processors

Processor SDK RTOS (PSDK RTOS) can be used together with either Processor SDK Linux (PSDK Linux) or Processor SDK QNX (PSDK QNX) to form a multi-processor software development platform for DRA821 SoCs within TI’s Jacinto™ platform. The SDK provides a comprehensive set of software (...)

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IDE, configuración, compilador o depurador

CCSTUDIO — Entorno de desarrollo integrado (IDE) de Code Composer Studio™

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Guía del usuario: PDF | HTML
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IDE, configuración, compilador o depurador

DDR-CONFIG-J7200 — DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
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SYSCONFIG — Standalone desktop version of SysConfig

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Sistema operativo (SO)

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Sistema operativo (SO)

GHS-3P-UVELOSITY — Green Hills Software u-velOSity Safety RTOS

The µ-velOSity™ Safety RTOS is the smallest of Green Hills Software's real-time operating systems and was designed especially for microcontrollers. It supports a wide range of TI processor families using the Arm® Cortex-M or Cortex-R cores as a main CPU or as a co-processors (...)
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Soporte de software

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Modelo de simulación

J7200 DRA821 BSDL Model

SPRM776.ZIP (10 KB) - BSDL Model
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Modelo de simulación

J7200 DRA821 IBIS Model

SPRM775.ZIP (2294 KB) - IBIS Model
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Modelo de simulación

J7200 DRA821 Thermal Model

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Esquema: PDF
Encapsulado Pines Símbolos CAD, huellas y modelos 3D
FCBGA (ALM) 433 Ultra Librarian
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Pedidos y calidad

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  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL)/reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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  • Lugar de fabricación
  • Lugar de ensamblaje

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