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DS90C365A

ACTIVO

Transmisor LVDS programable de +3.3 V de enlace de pantalla plana de 18 bits y 87.5 MHz

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DS90C365A

ACTIVO
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Detalles del producto

Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
Protocols Catalog Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365
  • No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered.
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread.
  • “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high.
  • 18 to 87.5 MHz shift clock support
  • Tx power consumption < 146 mW (typ) at 87.5 MHz Grayscale
  • Tx Power-down mode < 37 uW (typ)
  • Supports VGA, SVGA, XGA, SXGA (dual pixel), SXGA+ (dual pixel), UXGA (dual pixel).
  • Narrow bus reduces cable size and cost
  • Up to 1.785 Gbps throughput
  • Up to 223.125 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low profile 48-lead TSSOP package

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

  • Pin-to-pin compatible to DS90C363, DS90C363A and DS90C365
  • No special start-up sequence required between clock/data and /PD pins. Input signals (clock and data) can be applied either before or after the device is powered.
  • Support Spread Spectrum Clocking up to 100kHz frequency modulation & deviations of ±2.5% center spread or -5% down spread.
  • “Input Clock Detection” feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high.
  • 18 to 87.5 MHz shift clock support
  • Tx power consumption < 146 mW (typ) at 87.5 MHz Grayscale
  • Tx Power-down mode < 37 uW (typ)
  • Supports VGA, SVGA, XGA, SXGA (dual pixel), SXGA+ (dual pixel), UXGA (dual pixel).
  • Narrow bus reduces cable size and cost
  • Up to 1.785 Gbps throughput
  • Up to 223.125 Megabytes/sec bandwidth
  • 345 mV (typ) swing LVDS devices for low EMI
  • PLL requires no external components
  • Compliant to TIA/EIA-644 LVDS standard
  • Low profile 48-lead TSSOP package

All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.

The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters.

The DS90C365A transmitter converts 21 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21 bits RGB of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 21 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5 Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 229.687 Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spead Spectrum Clocking support..

The DS90C365A is a pin to pin compatible replacement for DS90C363, DS90C363A and DS90C365. The DS90C365A has additional features and improvements making it an ideal replacement for DS90C363, DS90C363A and DS90C365. family of LVDS Transmitters.

The DS90C365A transmitter converts 21 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over the fourth LVDS link. Every cycle of the transmit clock 21 bits RGB of input data are sampled and transmitted. At a transmit clock frequency of 87.5 MHz, 21 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 612.5 Mbps per LVDS data channel. Using a 87.5 MHz clock, the data throughput is 229.687 Mbytes/sec. This transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe FPDLink Receiver without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high-speed TTL interfaces with added Spead Spectrum Clocking support..
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DS90C365A 3.3V Prog LVDS Transm 18-Bit FPD Link-87.5 MHz datasheet (Rev. I) 12/04/2013
Nota sobre la aplicación High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 9/11/2018
Nota sobre la aplicación How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29/06/2018
Nota sobre la aplicación AN-1032 An Introduction to FPD-Link (Rev. C) 8/08/2017
Nota sobre la aplicación Receiver Skew Margin for Channel Link I and FPD Link I Devices PDF | HTML 13/01/2016
Nota sobre la aplicación TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15/05/2004
Nota sobre la aplicación AN-1056 STN Application Using FPD-Link 14/05/2004
Nota sobre la aplicación AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14/05/2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

FLINK3V8BT-85 — Kit de evaluación para la familia FPD-Link de dispositivos LVDS serializadores y deserializadores

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

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