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Serializadores-deserializadores de alta velocidad
Serializadores-deserializadores FPD-Link

DS90CF363B

ACTIVO

Transmisor LVDS de +3.3 V y flanco de bajada para enlace de pantalla plana (FPD) de 18 bits y 65 MHz

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DS90CF363B

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Detalles del producto

Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
Applications In-vehicle Infotainment (IVI) Input compatibility LVCMOS Function Serializer Output compatibility FPD-Link LVDS Color depth (bpp) 18 Features Low-EMI Point-to-Point Communication Rating Catalog Operating temperature range (°C) -10 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
  • "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
  • 18 to 68 MHz Shift Clock Support
  • Best–in–Class Set & Hold Times on TxINPUTs
  • Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-Down Mode < 37μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.3 Gbps Throughput
  • Up to 170 Megabytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-lead TSSOP Package
  • Improved Replacement for:
    • SN75LVDS84, DS90CF363A

All trademarks are the property of their respective owners.

  • No Special Start-up Sequence Required between Clock/Data and /PD Pins. Input Signal (Clock and Data) can be Applied Either Before or After the Device is Powered.
  • Support Spread Spectrum Clocking up to 100KHz Frequency Modulation & Deviations of ±2.5% Center Spread or −5% Down Spread.
  • "Input Clock Detection" Feature will Pull all LVDS Pairs to Logic Low when Input Clock is Missing and when /PD Pin is Logic High.
  • 18 to 68 MHz Shift Clock Support
  • Best–in–Class Set & Hold Times on TxINPUTs
  • Tx Power Consumption < 130 mW (typ) @65MHz Grayscale
  • 40% Less Power Dissipation than BiCMOS Alternatives
  • Tx Power-Down Mode < 37μW (typ)
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • Narrow Bus Reduces Cable Size and Cost
  • Up to 1.3 Gbps Throughput
  • Up to 170 Megabytes/sec Bandwidth
  • 345 mV (typ) Swing LVDS Devices for Low EMI
  • PLL Requires no External Components
  • Compatible with TIA/EIA-644 LVDS Standard
  • Low Profile 48-lead TSSOP Package
  • Improved Replacement for:
    • SN75LVDS84, DS90CF363A

All trademarks are the property of their respective owners.

The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.

The DS90CF363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90CF363B is fixed as a Falling edge strobe transmitter and will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.

This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
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Documentación técnica

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Documentación principal Tipo Título Opciones de formato Descargar la versión más reciente en inglés Fecha
* Hoja de datos DS90CF363B 3.3V Prog LVDS Transm 18-Bit FPDLink -65 MHz datasheet (Rev. D) 17/04/2013
Nota sobre la aplicación High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs 9/11/2018
Nota sobre la aplicación How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) 29/06/2018
Nota sobre la aplicación AN-1032 An Introduction to FPD-Link (Rev. C) 8/08/2017
Nota sobre la aplicación Receiver Skew Margin for Channel Link I and FPD Link I Devices PDF | HTML 13/01/2016
Nota sobre la aplicación TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map 15/05/2004
Nota sobre la aplicación AN-1056 STN Application Using FPD-Link 14/05/2004
Nota sobre la aplicación AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines 14/05/2004

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

FLINK3V8BT-85 — Kit de evaluación para la familia FPD-Link de dispositivos LVDS serializadores y deserializadores

The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.

The transmitter board accepts (...)

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