SN74ABT18245A

Name: SN74ABT18245A
Brand: TI
SKU: SN74ABT18245A
Price: 4.675 USD

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Dispositivos de prueba de exploración con transceptores de bus de 18 bits

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Hoja de datos

document-pdfAcrobat Scan Test Devices With 18-Bit Bus Transceivers datasheet (Rev. H) (Inglés)

SN74ABT18245A

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Detalles del producto

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

18

IOL (max) (mA)

64

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

ABT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

Supply voltage (min) (V)

4.5

Supply voltage (max) (V)

5.5

Number of channels

18

IOL (max) (mA)

64

IOH (max) (mA)

-32

Input type

TTL-Compatible CMOS

Output type

3-State

Features

Partial power down (Ioff), Very high speed (tpd 5-10ns)

Technology family

ABT

Rating

Catalog

Operating temperature range (°C)

-40 to 85

SSOP (DL)

56

190.647 mm² 18.42 x 10.35

TSSOP (DGG)

56

113.4 mm² 14 x 8.1

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Members of the Texas Instruments Widebus^TM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPE^TM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

Members of the Texas Instruments SCOPE^TM Family of Testability Products
Members of the Texas Instruments Widebus^TM Family
Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
SCOPE^TM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions, CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
State-of-the-Art EPIC-II B^TM BiCMOS Design Significantly Reduces Power Dissipation
Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages

SCOPE, Widebus, and EPIC-IIB are trademarks of Texas Instruments Incorporated.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPE^TM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

The 'ABT18245A scan test devices with 18-bit bus transceivers are members of the Texas Instruments SCOPE^TM testability integrated-
circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.

In the normal mode, these devices are 18-bit noninverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self-test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPE^TM bus transceivers.

Data flow is controlled by the direction-control (DIR) and output-enable (OE\) inputs. Data transmission is allowed from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at DIR. OE\ can be used to disable the device so that the buses are effectively isolated.

In the test mode, the normal operation of the SCOPE^TM bus transceivers is inhibited and the test circuitry is enabled to observe and control the input/output (I/O) boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.

Four dedicated test pins observe and control the operation of the test circuitry: test-data input (TDI), test-data output (TDO), test-mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.

The SN54ABT18245A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT18245A is characterized for operation from -40°C to 85°C.

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Documentación técnica

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	Tipo	Título	Fecha
*	Data sheet	Scan Test Devices With 18-Bit Bus Transceivers datasheet (Rev. H)	19 feb 1999
	Application note	Implications of Slow or Floating CMOS Inputs (Rev. E)	26 jul 2021
	Selection guide	Logic Guide (Rev. AB)	12 jun 2017
	Application note	Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)	02 dic 2015
	User guide	LOGIC Pocket Data Book (Rev. B)	16 ene 2007
	EVM User's guide	LASP Demo Board User's Guide	01 nov 2005
	Application note	Programming CPLDs Via the 'LVT8986 LASP	01 nov 2005
	Application note	Semiconductor Packing Material Electrostatic Discharge (ESD) Protection	08 jul 2004
	Application note	Selecting the Right Level Translation Solution (Rev. A)	22 jun 2004
	Application note	Quad Flatpack No-Lead Logic Packages (Rev. D)	16 feb 2004
	Application note	TI IBIS File Creation, Validation, and Distribution Processes	29 ago 2002
	Application note	Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices	10 may 2002
	Selection guide	Advanced Bus Interface Logic Selection Guide	09 ene 2001
	Application note	Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A)	01 ago 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Characterization Information (Rev. B)	01 jun 1997
	Application note	Designing With Logic (Rev. C)	01 jun 1997
	Application note	Advanced BiCMOS Technology (ABT) Logic Enables Optimal System Design (Rev. A)	01 mar 1997
	Application note	Family of Curves Demonstrating Output Skews for Advanced BiCMOS Devices (Rev. A)	01 dic 1996
	Application note	Input and Output Characteristics of Digital Integrated Circuits	01 oct 1996
	Application note	Live Insertion	01 oct 1996
	Application note	Understanding Advanced Bus-Interface Products Design Guide	01 may 1996

Diseño y desarrollo

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