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SN74LVC1G04-Q1

ACTIVO

Inversor de 1.65 V a 5.5 V de calidad automotriz

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SN74LVC1G04-Q1

ACTIVO
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Detalles del producto

Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family LVC Rating Automotive Operating temperature range (°C) -40 to 125
Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Technology family LVC Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-SC70 (DCK) 5 4.2 mm² 2 x 2.1
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified with the Following Results
    • Device Temperature Grade 1:
      –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESG Classification Level C4B
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015;
    Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 3.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Qualified for Automotive Applications
  • AEC-Q100 Qualified with the Following Results
    • Device Temperature Grade 1:
      –40°C to 125°C Ambient Operating Temperature Range
    • Device HBM ESD Classification Level H2
    • Device CDM ESG Classification Level C4B
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015;
    Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 3.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II

This single inverter gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G04 performs the Boolean function Y = A.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This single inverter gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G04 performs the Boolean function Y = A.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Documentación técnica

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Tipo Título Fecha
* Data sheet Single Inverter Gate, SN74LVC1G04-Q1 datasheet (Rev. D) 03 ene 2013
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Functional safety information SN74LVC1G04-Q1 Functional Safety FIT Rate and Failure Mode Distribution 30 dic 2019
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
More literature Automotive Logic Devices Brochure 27 ago 2014
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

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Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
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Modelo de simulación

HSPICE Model for SN74LVC1G04

SCEJ180.ZIP (86 KB) - HSpice Model
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Modelo de simulación

SN74LVC1G04 Behavioral SPICE Model

SCEM644.ZIP (7 KB) - PSpice Model
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Modelo de simulación

SN74LVC1G04 IBIS Model (Rev. C)

SCEM216C.ZIP (45 KB) - IBIS Model
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Diseños de referencia

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Esquema: PDF
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Design guide: PDF
Esquema: PDF
Diseños de referencia

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This reference design provides a modular battery test solution allowing users to have the flexibility to test batteries at different current levels with one design. This design leverages the TIDA-01041 reference design by providing two 100-A battery testers that can work independently or be (...)
Design guide: PDF
Esquema: PDF
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Design guide: PDF
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Paquete Pasadores Descargar
SOT-23 (DBV) 5 Ver opciones
SOT-SC70 (DCK) 5 Ver opciones
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Pedidos y calidad

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  • RoHS
  • REACH
  • Marcado del dispositivo
  • Acabado de plomo/material de la bola
  • Clasificación de nivel de sensibilidad a la humedad (MSL) / reflujo máximo
  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
Información incluida:
  • Lugar de fabricación
  • Lugar de ensamblaje

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