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Compuertas lógicas
Compuertas XOR (OR exclusiva)

SN74LVC2G86

ACTIVO

Puertas XOR (OR exclusivo) de 2 canales, 2 entradas, 1.65 V a 5.5 V

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SN74LVC2G86

ACTIVO
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Detalles del producto

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 Input type Standard CMOS IOH (max) (mA) -32 Output type Push-Pull Features Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 2 Inputs per channel 2 IOL (max) (mA) 32 Input type Standard CMOS IOH (max) (mA) -32 Output type Push-Pull Features Over-voltage tolerant Inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
DSBGA (YZP) 8 2.8125 mm² 2.25 x 1.25 SSOP (DCT) 8 11.8 mm² 2.95 x 4 VSSOP (DCU) 8 6.2 mm² 2 x 3.1
  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.7 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.

This dual 2-input exclusive-OR gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G86 performs the Boolean function Y = A ⊕ B or Y = AB + AB in positive logic.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

A common application is as a true/complement element. If the input is low, the other input is reproduced in true form at the output. If the input is high, the signal on the other input is reproduced inverted at the output.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols.
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SN74AUC2G86 ACTIVO Puertas XOR (OR exclusiva) de alta velocidad, de 2 canales, 2 entradas, de 0.8 V a 2.7 V Smaller voltage range (0.8V to 2.7V), shorter average propagation delay (1.7ns)

Documentación técnica

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Tipo Título Fecha
* Data sheet Dual 2-Input Exclusive-OR Gate, SN74LVC2G86 datasheet (Rev. I) 10 dic 2013
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 jul 2021
Selection guide Little Logic Guide 2018 (Rev. G) 06 jul 2018
Selection guide Logic Guide (Rev. AB) 12 jun 2017
Application note How to Select Little Logic (Rev. A) 26 jul 2016
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 dic 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 ene 2007
Product overview Design Summary for WCSP Little Logic (Rev. B) 04 nov 2004
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 jun 2004
User guide Signal Switch Data Book (Rev. A) 14 nov 2003
Application note Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 dic 2002
Application note Texas Instruments Little Logic Application Report 01 nov 2002
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 ago 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 may 2002
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 may 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 mar 2002
Application note Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 dic 1997
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 ago 1997
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 jun 1997
Application note LVC Characterization Information 01 dic 1996
Application note Input and Output Characteristics of Digital Integrated Circuits 01 oct 1996
Application note Live Insertion 01 oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 may 1996

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

5-8-LOGIC-EVM — Módulo de evaluación lógica genérico para encapsulados DCK, DCT, DCU, DRL y DBV de 5 a 8 pines

Módulo de evaluación (EVM) flexible diseñado para admitir cualquier dispositivo que tenga un encapsulado DCK, DCT, DCU, DRL o DBV en un recuento de 5 a 8 pines.
Guía del usuario: PDF
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Modelo de simulación

SN74LVC2G86 Behavioral SPICE Model

SCEM609.ZIP (7 KB) - PSpice Model
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Modelo de simulación

SN74LVC2G86 IBIS Model (Rev. A)

SCEM300A.ZIP (43 KB) - IBIS Model
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Diseños de referencia

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TIDA-00548 is an isolated dual-channel 4- to 20-mA analog input reference design, which can be used as a sub-part for functional safety programmable logic controllers (PLCs). This reference design delivers digitized input values using a 32-bit high-performance analog-to-digital converter (ADC). (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

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This eight-channel, parallel, 2-A, high-side, digital output reference design for factory automation applications like PLCs shows the diagnostic features and the power density of new Texas Instruments high-side driver components (such as TPS27S100). Each output can individually measure the output (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-01333 — Diseño de referencia de módulo aislado de entrada analógica, alta tensión y 8 canales con ISOW7841

The TIDA-01333 isolated high voltage analog input module reference design has eight channels supporting both, voltage and current measurement. In addition, 4 channels support common-mode voltages up to ±160V. Isolation of +5V line and the Serial Peripheral Interface  (SPI) (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00550 — Diseño de referencia del módulo de entrada analógica universal aislado de canal a canal doble para P

TIDA-00550, a dual channel-to-channel isolated universal analog input module reference design for programmable logic controllers (PLCs), combines precision and flexibility. This reference design, used in conjunction with sensor transmitters, can measure standard input voltages and currents as (...)
Design guide: PDF
Esquema: PDF
Diseños de referencia

TIDA-00560 — Diseño de referencia del controlador LED de estado de 16 canales para los módulos PLC

The objective of TIDA-00560 is to demonstrate a multi-channel LED driver as required in PLC I/O modules to indicate the status of several analog, digital input and output channels. Important requirements for low static current, low component count, minimal PCB requirements and an integrated LED (...)
Guía del usuario: PDF
Esquema: PDF
Diseños de referencia

TIDA-00764 — Diseño de referencia del módulo aislado de entrada analógica, alta tensión y 8 canales

This reference design is a high-voltage analog input module with eight channels. Each channel can be used for both voltage and current measurement. The design uses 16-bit analog-to-digital converter (ADC) ADS8681 that can handle input voltage of up to ±12.288 V. This make any (...)
Design guide: PDF
Esquema: PDF
Paquete Pasadores Descargar
DSBGA (YZP) 8 Ver opciones
SSOP (DCT) 8 Ver opciones
VSSOP (DCU) 8 Ver opciones
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Pedidos y calidad

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  • Estimaciones de tiempo medio entre fallas (MTBF)/fallas en el tiempo (FIT)
  • Contenido del material
  • Resumen de calificaciones
  • Monitoreo continuo de confiabilidad
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