The TPS7A8300 is a low-noise (6 µVRMS), low-dropout voltage regulator (LDO) capable of sourcing a 2-A load with only 125 mV of maximum dropout.
The TPS7A8300 output voltages are fully user-adjustable (up to 3.95 V) using a printed circuit board (PCB) layout without the need of external resistors, thus reducing overall component count. For higher output voltage applications, the device achieves output voltages up to 5 V with the use of external resistors. The device supports very low input voltages (down to 1.1 V) with the use of an additional BIAS rail.
With very high accuracy (1% over line, load, and temperature), remote sensing, and soft-start capabilities to reduce inrush current, the TPS7A8300 is ideal for powering high-current, low-voltage devices such as high-end microprocessors and field-programmable gate arrays (FPGAs).
The TPS7A8300 is designed to power-up noise-sensitive components in high-speed communication applications. The very low-noise, 6-µVRMS device output and high broad-bandwidth PSRR (40 dB at 1 MHz) minimizes phase noise and clock jitter in high-frequency signals. These features maximize performance of clocking devices, analog-to-digital converters (ADCs), and digital-to-analog converters (DACs).
For applications where positive and negative low-noise rails are required, consider TI’s TPS7A33 family of negative high-voltage, ultralow-noise linear regulators.
Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.
The ADS54J40EVM is an evaluation module (EVM) that allows for the evaluation of Texas Instruments’ ADS54J40 and LMK04828 clock jitter cleaner. The ADS54J40 is a low power, 14-bit, 1-GSPS analog to digital converter (ADC) with a buffered analog input and outputs featuring a JESD204B interface. (...)
El ADS54J69EVM es un módulo de evaluación (EVM) que permite evaluar el limpiador de fluctuaciones de reloj ADS54J69 y LMK04828 de Texas Instruments. El ADS54J69 es un convertidor analógico a digital (ADC) de 16 bits y 500 MSPS de baja potencia con una entrada analógica con búfer y salidas con (...)
The TPS7A8300EVM-579 evaluation module is designed for a typical configuration to evaluate the operation and performance of the TPS7A8300, 2-A low dropout voltage regulator for high speed communication systems.
The EVM circuit board is configured to be a reference design for engineering applications (...)
Nuestra placa de experimentación TI-PMLK LDO forma parte de la serie TI Power Management Lab Kit (TI-PMLK). La serie TI-PMLK ofrece aprendizaje práctico para reforzar el conocimiento de la fuente de alimentación. El formato modular le permite personalizar la experiencia de la serie TI-PMLK de forma (...)
The parallel low-dropout (LDO) calculator is a Microsoft® Excel®-based tool that provides worst-case analysis for parallel LDO regulators using ballast resistors. The tool helps the user identify the minimum number of parallel LDO regulators required and optimum ballast resistance for a (...)
Utilice nuestra herramienta de selección de diseños de referencia para revisar e identificar los diseños que mejor se adaptan a su aplicación y parámetros.
| Encapsulado | Pines | Símbolos CAD, huellas y modelos 3D |
|---|---|---|
| VQFN (RGR) | 20 | Ultra Librarian |
| VQFN (RGW) | 20 | Ultra Librarian |
Los productos recomendados pueden tener parámetros, módulos de evaluación o diseños de referencia relacionados con este producto de TI.
El contenido lo proporcionan “tal como está” TI y los colaboradores de la comunidad y no constituye especificaciones de TI. Consulte los términos de uso.
Si tiene preguntas sobre la calidad, el paquete o el pedido de productos de TI, consulte el soporte de TI.
Parallel LDO Calculator using ballast resistors
Initial Release