ホーム インターフェイス I2C & I3C ICs I2C & I3C level shifters, buffers & hubs

PCA9518

アクティブ

5 チャネル、双方向、3V ~ 3.6V、拡張可能 400kHz I2C/SMBus バッファ / ハブ

製品詳細

Features Reset pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 3 VCCA (max) (V) 3.6 VCCB (min) (V) 3 VCCB (max) (V) 3.6 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (°C) -40 to 85
Features Reset pin Protocols I2C Frequency (max) (MHz) 0.4 VCCA (min) (V) 3 VCCA (max) (V) 3.6 VCCB (min) (V) 3 VCCB (max) (V) 3.6 Supply restrictions VCC Single Supply Rating Catalog Operating temperature range (°C) -40 to 85
SOIC (DW) 20 131.84 mm² 12.8 x 10.3 SSOP (DB) 20 56.16 mm² 7.2 x 7.8 SSOP (DBQ) 20 51.9 mm² 8.65 x 6 TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Expandable Five-Channel Bidirectional Buffer
  • 400-kHz Fast I2C Bus
  • Operating VCC Range of 3 V to 3.6 V
  • 5-V Tolerant I2C and Enable Input Pins to Support Mixed-Mode Signal Operation
  • Active-High Individual Repeater Enable Inputs
  • Open-Drain Input/Outputs
  • Lockup-Free Operation
  • Supports Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • I2C Bus and SMBus Compatible
  • Latchup Performance Exceeds 100 mA Per JESD 78
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

  • Expandable Five-Channel Bidirectional Buffer
  • 400-kHz Fast I2C Bus
  • Operating VCC Range of 3 V to 3.6 V
  • 5-V Tolerant I2C and Enable Input Pins to Support Mixed-Mode Signal Operation
  • Active-High Individual Repeater Enable Inputs
  • Open-Drain Input/Outputs
  • Lockup-Free Operation
  • Supports Multiple Masters
  • Powered-Off High-Impedance I2C Pins
  • I2C Bus and SMBus Compatible
  • Latchup Performance Exceeds 100 mA Per JESD 78
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

All trademarks are the property of their respective owners.

The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance.

The PCA9518 does not support clock stretching across the repeater.

The device is designed for 3-V to 3.6-V VCC operation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater.

The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lockup condition from occurring when the input low condition is released.

A PCA9518 cluster cannot be put in series with a repeater such as the PCA9515 or another PCA9518 cluster, as the design does not allow this configuration. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster using the EXPxxxx pins that allow the I2C signals to be sent or received from one PCA9518 to another PCA9518 within the cluster. Because there is no direction pin, slightly different valid low voltage levels are used to avoid lockup conditions between the input and the output of individual repeaters in the cluster. A valid low applied at the input of any of the PCA9518 devices is propagated as a buffered low, with a slightly higher value, to all enabled outputs in the PCA9518 cluster. When this buffered low is applied to another repeater or separate PCA9518 cluster (not connected via the EXPxxxx pins) in series, the second repeater or PCA9518 cluster does not recognize it as a regular low and does not propagate it as a buffered low again. For this reason, the PCA9518 should not be put in series with other repeater or PCA9518 clusters.

The PCA9518 has five multidirectional open-drain buffers designed to support the standard low-level-contention arbitration of the I2C bus. Except during arbitration, the PCA9518 acts like a pair of noninverting open-drain buffers, one for SDA and one for SCL.

There is an internal power-on-reset circuit (VPOR) that allows for an initial condition and the ramping of VCC to set the internal logic.

As with the standard I2C system, pullup resistors are required on each SDAn and SCLn to provide the logic high levels on the buffered bus. The size of these pullup resistors depends on the system, but it is essential that each side of the repeater have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.

The PCA9518 is an expandable five-channel bidirectional buffer for I2C and SMBus applications. The I2C protocol requires a maximum bus capacitance of 400 pF, which is derived from the number of devices on the I2C bus and the bus length. The PCA9518 overcomes this restriction by separating and buffering the I2C data (SDA) and clock (SCL) lines into multiple groups of 400-pF segments. Any segment-to-segment transition sees only one repeater delay. Each PCA9518 can communicate with other PCA9518 hubs through a 4-wire inter-hub expansion bus. Using multiple PCA9518 parts, any width hub (in multiples of five) can be implemented using the expansion pins, with only one repeater delay and no functional degradation of the system performance.

The PCA9518 does not support clock stretching across the repeater.

The device is designed for 3-V to 3.6-V VCC operation, but it has 5-V tolerant I2C and enable (EN) input pins. This feature allows for translation from 3 V to 5 V between a master and slave. The enable pin also can be used to electrically isolate a repeater segment from the I2C bus. This is useful in cases where one segment needs to run at 100 kHz while the rest of the system is at 400 kHz. If the master is running at 400 kHz, the maximum system operating frequency may be less than 400 kHz, because of the delays added by the repeater.

The output low levels for each internal buffer are approximately 0.5 V, but the input voltage of each internal buffer must be 70 mV or more below the output low level, when the output internally is driven low. This prevents a lockup condition from occurring when the input low condition is released.

A PCA9518 cluster cannot be put in series with a repeater such as the PCA9515 or another PCA9518 cluster, as the design does not allow this configuration. Multiple PCA9518 devices can be grouped with other PCA9518 devices into any size cluster using the EXPxxxx pins that allow the I2C signals to be sent or received from one PCA9518 to another PCA9518 within the cluster. Because there is no direction pin, slightly different valid low voltage levels are used to avoid lockup conditions between the input and the output of individual repeaters in the cluster. A valid low applied at the input of any of the PCA9518 devices is propagated as a buffered low, with a slightly higher value, to all enabled outputs in the PCA9518 cluster. When this buffered low is applied to another repeater or separate PCA9518 cluster (not connected via the EXPxxxx pins) in series, the second repeater or PCA9518 cluster does not recognize it as a regular low and does not propagate it as a buffered low again. For this reason, the PCA9518 should not be put in series with other repeater or PCA9518 clusters.

The PCA9518 has five multidirectional open-drain buffers designed to support the standard low-level-contention arbitration of the I2C bus. Except during arbitration, the PCA9518 acts like a pair of noninverting open-drain buffers, one for SDA and one for SCL.

There is an internal power-on-reset circuit (VPOR) that allows for an initial condition and the ramping of VCC to set the internal logic.

As with the standard I2C system, pullup resistors are required on each SDAn and SCLn to provide the logic high levels on the buffered bus. The size of these pullup resistors depends on the system, but it is essential that each side of the repeater have a pullup resistor. The device is designed to work with standard-mode and fast-mode I2C devices in addition to SMBus devices. Standard-mode I2C devices only specify 3 mA in a generic I2C system where standard-mode devices and multiple masters are possible.

ダウンロード 字幕付きのビデオを表示 ビデオ

お客様が関心を持ちそうな類似品

open-in-new 代替品と比較
比較対象デバイスと類似の機能
TCA9545A アクティブ 割り込み、リセット / 電圧レベル・シフト機能搭載、4 チャネル、1.65V ~ 5.5V I2C/SMBus スイッチ This device has similar functionality in an equivalent package with a wider supply voltage range, reset and interrupt pin capabilities, and improved performance.

技術資料

star =TI が選定したこの製品の主要ドキュメント
結果が見つかりませんでした。検索条件をクリアしてから、再度検索を試してください。
12 をすべて表示
種類 タイトル 最新の英語版をダウンロード 日付
* データシート PCA9518 Expandable Five-Channel I2C Hub データシート (Rev. C) 2014年 6月 12日
アプリケーション・ノート Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
アプリケーション・ノート I2C Dynamic Addressing 2019年 4月 25日
セレクション・ガイド Logic Guide (Rev. AB) 2017年 6月 12日
アプリケーション・ノート Choosing the Correct I2C Device for New Designs PDF | HTML 2016年 9月 7日
アプリケーション・ノート Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
アプリケーション・ノート Understanding the I2C Bus PDF | HTML 2015年 6月 30日
アプリケーション・ノート Maximum Clock Frequency of I2C Bus Using Repeaters 2015年 5月 15日
アプリケーション・ノート I2C Bus Pull-Up Resistor Calculation PDF | HTML 2015年 2月 13日
セレクション・ガイド ロジック・ガイド (Rev. AA 翻訳版) 最新英語版 (Rev.AB) 2014年 11月 6日
アプリケーション・ノート Programming Fun Lights With TI's TCA6507 2007年 11月 30日
アプリケーション・ノート Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
シミュレーション・ツール

TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

TINA-TI は、DC 解析、過渡解析、周波数ドメイン解析など、SPICE の標準的な機能すべてを搭載しています。TINA には多彩な後処理機能があり、結果を必要なフォーマットにすることができます。仮想計測機能を使用すると、入力波形を選択し、回路ノードの電圧や波形を仮想的に測定することができます。TINA の回路キャプチャ機能は非常に直観的であり、「クイックスタート」を実現できます。

TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー ガイド: PDF
英語版 (Rev.A): PDF
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
SOIC (DW) 20 Ultra Librarian
SSOP (DB) 20 Ultra Librarian
SSOP (DBQ) 20 Ultra Librarian
TSSOP (PW) 20 Ultra Librarian

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用原材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報:
  • ファブの拠点
  • 組み立てを実施した拠点

推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス デザインが存在する可能性があります。

サポートとトレーニング

TI E2E™ フォーラムでは、TI のエンジニアからの技術サポートを提供

コンテンツは、TI 投稿者やコミュニティ投稿者によって「現状のまま」提供されるもので、TI による仕様の追加を意図するものではありません。使用条件をご確認ください。

TI 製品の品質、パッケージ、ご注文に関するお問い合わせは、TI サポートをご覧ください。​​​​​​​​​​​​​​

ビデオ