製品詳細

Operating temperature range (C) -40 to 85
Operating temperature range (C) -40 to 85
FCBGA (CTR) 144 169 mm² 13 x 13
  • Automatic Digital Multiplexing/De-Multiplexing of 4,
    3, or 2 Independent Lower-Speed Gigabit Serial Lines
    into a Single Higher-Speed Gigabit Serial Line
  • 4 × (0.25 to 2.5 Gbps) to 1 × (1 to 10 Gbps) Multiplexing
  • 3 × (0.5 to 3.33 Gbps) to 1× (1.5 to 10 Gbps)
  • 2 × (0.5 to 5 Gbps) to 1 × (1 to 10 Gbps)
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Programmable Per Channel Lane Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization
    on Both Low Speed and High Speed Sides
  • 8B/10B ENDEC Coding Support
  • Raw (unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Programmable High Speed Scrambling/Descrambling Functions
    Improve Serial Link Transition Density and Reduce Spectral Peaks
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800mW per Channel (typ)
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable Lane Marker Character
  • Support for Programmable HS/LS 10-Bit Alignment Character
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package
  • Automatic Digital Multiplexing/De-Multiplexing of 4,
    3, or 2 Independent Lower-Speed Gigabit Serial Lines
    into a Single Higher-Speed Gigabit Serial Line
  • 4 × (0.25 to 2.5 Gbps) to 1 × (1 to 10 Gbps) Multiplexing
  • 3 × (0.5 to 3.33 Gbps) to 1× (1.5 to 10 Gbps)
  • 2 × (0.5 to 5 Gbps) to 1 × (1 to 10 Gbps)
  • 1 × (0.5 to 2.5 Gbps) to 1 × (0.5 to 2.5 Gbps)
  • Programmable Per Channel Lane Switching
  • Wide Data Rate Range for Multiple Application Support
  • Transmit De-Emphasis and Adaptive Receiver Equalization
    on Both Low Speed and High Speed Sides
  • 8B/10B ENDEC Coding Support
  • Raw (unencoded) Data Support
  • Core Supply 1V; I/O: 1.5V/1.8V
  • Programmable High Speed Scrambling/Descrambling Functions
    Improve Serial Link Transition Density and Reduce Spectral Peaks
  • Superior Signal Integrity Performance
  • Low Power Operation: < 800mW per Channel (typ)
  • Flexible Clocking
  • Multi Drive Capability (SFP+, backplane, cable)
  • Support for Programmable Lane Marker Character
  • Support for Programmable HS/LS 10-Bit Alignment Character
  • Wide Range of Built-in Test Patterns
  • 144-pin, 13mmx13mm FCBGA Package

The TLK10022 is a dual-channel multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

Each channel of the TLK10022 has a low-speed interface which can accommodate one, two, three, or four bidirectional serial links running at rates from 250 Mbps to 5 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces (one per channel, bidirectional) can operate at rates from 1 Gbps to 10 Gbps. When a channel is configured for a certain multiplexing ratio (1-to-1, 2-to-1, 3-to-1, or 4-to-1), the high speed side will operate at a fixed multiple of the low speed rate (e.g., four times faster for 4-to-1 mode) regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so the TX and RX can operates in different modes (this excludes 3:1 mode which requires both the TX and RX path to run in the same mode). This independence is restricted to using the same low speed line rate. For example, the TX can operate at 4 × 2.5 Gbps while RX operates at 1 x 2.5 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The TLK10022 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10022 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

The TLK10022 is a dual-channel multi-rate link aggregator intended for use in high-speed bi-directional point-to-point data transmission systems. The device allows for a reduction in the number of physical links required for a certain data throughput by multiplexing multiple lower-rate serial links into higher-rate serial links.

Each channel of the TLK10022 has a low-speed interface which can accommodate one, two, three, or four bidirectional serial links running at rates from 250 Mbps to 5 Gbps (maximum of 10 Gbps total throughput). The device’s high speed interfaces (one per channel, bidirectional) can operate at rates from 1 Gbps to 10 Gbps. When a channel is configured for a certain multiplexing ratio (1-to-1, 2-to-1, 3-to-1, or 4-to-1), the high speed side will operate at a fixed multiple of the low speed rate (e.g., four times faster for 4-to-1 mode) regardless of the number of lanes connected. Filler data will be placed on any unused lanes in order to keep the interleaved lane ordering constant. This allows for low speed lanes to be hot swapped during normal operation without requiring a change in configuration.

The device has multiple interleaving/de-interleaving schemes that may be used depending on the data type. These schemes allow for the low speed lane ordering to be recovered after the lanes are transmitted over a single high-speed link. There is also a programmable scrambling/de-scrambling function available to help ensure that the high-speed data has suitable properties for transmission (i.e., sufficient transition density for clock recovery and DC balance over time) even for non-ideal input data.

A 1:1 mode is also supported for data rates ranging from 0.5 Gbps to 2.5 Gbps, whereby both low speed and high speed are rate matched. The TX and RX datapaths are also independent, so the TX and RX can operates in different modes (this excludes 3:1 mode which requires both the TX and RX path to run in the same mode). This independence is restricted to using the same low speed line rate. For example, the TX can operate at 4 × 2.5 Gbps while RX operates at 1 x 2.5 Gbps.

The individual Low Speed lanes may also operate at independent rates in byte interleave mode, provided they are operating at integer multiples. The High Speed line rate must be configured based on the fastest Low Speed line rate.

The TLK10022 has the ability to perform lane alignment on 2, 3, or 4 lanes with up to four bytes of lane de-skew.

Both the low speed and high speed side interfaces (transmitters and receivers) use CML signaling with integrated termination resistors and feature programmable transmitter de-emphasis levels and adaptive receive equalization to help compensate for media impairments at higher frequencies. The device’s serial transceivers used are capable of interfacing to optical modules as well as higher-loss connections such as PCB backplanes and controlled-impedance copper cabling.

To aid in system synchronization, the TLK10022 is capable of extracting clocking information from the serial input data streams and outputting a recovered clock signal. This recovered clock can be input to a jitter cleaner in order to provide a synchronized system clock. The device also has two reference clock input ports and a flexible internal PLL, allowing for various serial rates to be supported with a single reference clock input frequency.

The device has various built-in self-test features to aid with system validation and debugging. Among these are pattern generation and verification on all serial lanes as well as internal data loopback paths.

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技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート TLK10022 10Gbps DUAL-CHANNEL MULTI-RATE UNIVERSAL LINK AGGREGATOR データシート 2013年 11月 7日
技術記事 Get Connected: Data aggregation using a general purpose SerDes 2014年 12月 17日
アプリケーション・ノート Video Aggregation HD-SDI 2014年 10月 1日
アプリケーション・ノート Video Aggregation – Display Port Interface Application Sheet 2013年 12月 16日
ユーザー・ガイド TLK10022 and TLK10081 EVM GUI User's Guide 2013年 11月 8日
EVM ユーザー ガイド (英語) TLK10022 and TLK10081 EVM User's Guide 2013年 11月 8日

設計および開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページを表示してください。

評価ボード

TLK10022EVM — TLK10022EVM - マザーボード評価モジュール、10Gbps マルチレート・ユニバーサル・リンク・アグリゲータ用

This motherboard evaluation board for TLK10022 comes with custom-developed GUI and a detailed EVM user guide. The EVM along with the GUI, enable customers to configure the registers of all the channels independently and to debug the device. The user’s guide provides guidance on proper use of (...)

ユーザー・ガイド: PDF
評価基板 (EVM) 向けの GUI

TLK10022/81 EVM GUI Software

SLLC440.ZIP (37141 KB)
シミュレーション・モデル

TLK10022 Hspice Model

SLLM232.ZIP (9164 KB) - HSpice Model
シミュレーション・モデル

TLK10022 IBIS Model

SLLM231.ZIP (60 KB) - IBIS Model
シミュレーション・ツール

PSPICE-FOR-TI — TI Design / シミュレーション・ツール向け PSpice®

PSpice® for TI は、各種アナログ回路の機能評価に役立つ、設計とシミュレーション向けの環境です。設計とシミュレーションに適したこのフル機能スイートは、Cadence® のアナログ分析エンジンを使用しています。PSpice for TI は無償で使用でき、アナログや電源に関する TI の製品ラインアップを対象とする、業界でも有数の大規模なモデル・ライブラリが付属しているほか、選択された一部のアナログ動作モデルも利用できます。

設計とシミュレーション向けの環境である PSpice for TI (...)
シミュレーション・ツール

TINA-TI — SPICE ベースのアナログ・シミュレーション・プログラム

TINA-TI は、DC 解析、過渡解析、周波数ドメイン解析など、SPICE の標準的な機能すべてを搭載しています。TINA には多彩な後処理機能があり、結果を必要なフォーマットにすることができます。仮想計測機能を使用すると、入力波形を選択し、回路ノードの電圧や波形を仮想的に測定することができます。TINA の回路キャプチャ機能は非常に直観的であり、「クイックスタート」を実現できます。

TINA-TI をインストールするには、約 500MB が必要です。インストールは簡単です。必要に応じてアンインストールも可能です。(そのようなことはないと思いますが)

TINA は DesignSoft (...)

ユーザー・ガイド: PDF
英語版をダウンロード (Rev.A): PDF
リファレンス・デザイン

TIDA-00352 — SDI ビデオ アグリゲーション・リファレンス・デザイン

This verified reference design is a complete four channel SDI aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous HD-SDI sources together into one 5.94 Gbps serial link. The serial data is transferred via copper or optical fiber where a second TLK10022 is (...)
試験報告書: PDF
回路図: PDF
リファレンス・デザイン

TIDA-00309 — DisplayPort ビデオ 4:1 アグリゲーション・リファレンス・デザイン

This verified reference design is a complete four channel DisplayPort aggregation and de-aggregation solution. One TLK10022 is used to aggregate four synchronous DisplayPort (DP) sources together into one 10.8 Gbps serial link. The serial data is transferred via copper or optical fiber where a (...)
試験報告書: PDF
回路図: PDF
パッケージ ピン数 ダウンロード
FCBGA (CTR) 144 オプションの表示

購入と品質

記載されている情報:
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  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL rating / リフローピーク温度
  • MTBF/FIT 推定値
  • 材料 (内容)
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果

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