CD4521B

활성

CMOS 24단계 주파수 디바이더

지금 주문

데이터 시트

document-pdfAcrobat CD4521B TYPES datasheet (Rev. C) (영어)

CD4521B

활성

데이터 시트

지금 주문

제품 상세 정보

Function

Frequency divider

Bits (#)

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Features

Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

Function

Frequency divider

Bits (#)

4

Technology family

CD4000

Supply voltage (min) (V)

3

Supply voltage (max) (V)

18

Input type

Standard CMOS

Output type

Push-Pull

Features

Partial power down (Ioff), Standard speed (tpd > 50ns)

Operating temperature range (°C)

-55 to 125

Rating

Catalog

PDIP (N)

16

181.42 mm² 19.3 x 9.4

SOIC (D)

16

59.4 mm² 9.9 x 6

SOP (NS)

16

79.56 mm² 10.2 x 7.8

TSSOP (PW)

16

32 mm² 5 x 6.4

Reset disables the RC oscillator for low-power standby condition
V_DD’ and V_SS’ pins are brought out from the crystal oscillator to allow use of external resistors for low-power operation
Maximum input current of 1 µA at 18 V over full package-temperature range:
100 nA at 18 V and 25°C
Common reset
100% tested for 20-V quiescent current
5, 10 and 15 V parametric ratings
Standardized symmetrical output characteristics
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

Reset disables the RC oscillator for low-power standby condition
V_DD’ and V_SS’ pins are brought out from the crystal oscillator to allow use of external resistors for low-power operation
Maximum input current of 1 µA at 18 V over full package-temperature range:
100 nA at 18 V and 25°C
Common reset
100% tested for 20-V quiescent current
5, 10 and 15 V parametric ratings
Standardized symmetrical output characteristics
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

CD4521B consists of an oscillator section and 24 ripple-carry binary counter stages. The oscillator configuration (using IN1) allows design of either RC or crystal oscillator circuits. IN1 should be tied either HIGH or LOW when not in use. A HIGH on the RESET causes the counter to go to the all-0’s state and disables the oscillator. The count is advanced on the negative transition of IN1 (and IN2). A time-saving test mode is described in the Functional Test Sequence Table and in Fig. 6.

The CD4521B types are supplied in 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

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