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Technology family FCT Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
Technology family FCT Function Digital Multiplexer Configuration 2:1 Number of channels 4 Operating temperature range (°C) -40 to 85 Rating Catalog
SOIC (D) 16 59.4 mm² 9.9 x 6 SOIC (DW) 16 106.09 mm² 10.3 x 10.3 SSOP (DBQ) 16 29.4 mm² 4.9 x 6
  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • 3-State Outputs

  • Function, Pinout, and Drive Compatible With FCT and F Logic
  • Reduced VOH (Typically = 3.3 V) Version of Equivalent FCT Functions
  • Edge-Rate Control Circuitry for Significantly Improved Noise Characteristics
  • Ioff Supports Partial-Power-Down Mode Operation
  • Matched Rise and Fall Times
  • Fully Compatible With TTL Input and Output Logic Levels
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 64-mA Output Sink Current
    32-mA Output Source Current
  • 3-State Outputs

The CY74FCT257T has four identical two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The I0 inputs are selected when S is low, and the I1 inputs are selected when S is high. Data at the output is noninverted.

The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in the high-impedance state when the output-enable (OE\) input is high.

All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tied together. OE\ inputs must ensure that there is no overlap when outputs of 3-state devices are tied together.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The CY74FCT257T has four identical two-input multiplexers that select four bits of data from two sources under the control of a common data-select (S) input. The I0 inputs are selected when S is low, and the I1 inputs are selected when S is high. Data at the output is noninverted.

The CY74FCT257T is a logic implementation of a four-pole, two-position switch, where the position of the switch is determined by the logic levels at S. Outputs are in the high-impedance state when the output-enable (OE\) input is high.

All but one device must be in the high-impedance state to avoid currents exceeding the maximum ratings if outputs are tied together. OE\ inputs must ensure that there is no overlap when outputs of 3-state devices are tied together.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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관심 가지실만한 유사 제품

open-in-new 대안 비교
비교 대상 장치보다 업그레이드된 기능을 지원하는 즉각적 대체품
신규 SN74AHCT257 활성 Quadruple 2-line to 1-line data selectors/multiplexers with TTL inputs Larger voltage range (2V to 5.5V)
비교 대상 장치와 유사한 기능
CD74ACT257 활성 3상 출력을 지원하는 쿼드 2입력 비인버팅 멀티플렉서 Higher average drive strength (24mA)

기술 자료

star =TI에서 선정한 이 제품의 인기 문서
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9개 모두 보기
유형 직함 날짜
* Data sheet Quad 2-Input Multiplexer With 3-State Outputs datasheet (Rev. D) 2001/11/02
White paper Understanding Functional Safety FIT Base Failure Rate Estimates per IEC 62380 and SN 29500 (Rev. A) PDF | HTML 2024/04/30
Selection guide Logic Guide (Rev. AB) 2017/06/12
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015/12/02
User guide LOGIC Pocket Data Book (Rev. B) 2007/01/16
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004/07/08
Application note Selecting the Right Level Translation Solution (Rev. A) 2004/06/22
User guide CYFCT Parameter Measurement Information 2001/04/02
Selection guide Advanced Bus Interface Logic Selection Guide 2001/01/09

설계 및 개발

추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.

평가 보드

14-24-LOGIC-EVM — 14핀~24핀 D, DB, DGV, DW, DYY, NS 및 PW 패키지용 로직 제품 일반 평가 모듈

14-24-LOGIC-EVM 평가 모듈(EVM)은 14핀~24핀 D, DW, DB, NS, PW, DYY 또는 DGV 패키지에 있는 모든 로직 장치를 지원하도록 설계되었습니다.

사용 설명서: PDF | HTML
TI.com에서 구매 불가
패키지 CAD 기호, 풋프린트 및 3D 모델
SOIC (D) 16 Ultra Librarian
SOIC (DW) 16 Ultra Librarian
SSOP (DBQ) 16 Ultra Librarian

주문 및 품질

포함된 정보:
  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
포함된 정보:
  • 팹 위치
  • 조립 위치

지원 및 교육

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