DP83TG721R-Q1
- IEEE802.3bp 1000BASE-T1 compliant
- OA TC10 compliant, <20µA sleep current
- Local and remote wakeup and wake forwarding
- Advanced TSN
- IEEE 1588v2/802.1AS time synchronization
- Hardware time-stamping with integrated phase correction
- Highly accurate 1pps signal (±15ns)
- Audio clocking
- AVB IEEE 1722 media clock generation capability
- Phase synchronized wall clock output: 1KHz to 50MHz
- I2S and TDM8 SCLK/FSYNC/MCLK clock generation
- Open Alliance TC12 Interoperability and EMC compliant
- OA EMC compliant
- SAE J2962-3 EMC Compliant
- Integrated LPF on MDI pins
- MAC interfaces: RGMII and SGMII
- Supported I/O voltages: 3.3V, 2.5V, and 1.8V
- Pin compatible with TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs
- Single board design for 100BASE-T1 and 1000BASE-T1 with required BOM change
- Diagnostic toolkit
- Temperature, voltage, ESD monitor
- Data throughput calculator: inbuilt MAC packet generator, counter and error checker
- Signal quality indicator
- TDR based open and short cable fault detection
- Loopback modes
- AEC-Q100 qualified
- IEC61000-4-2 ESD: ±8kV contact discharge
The DP83TG721-Q1 is an IEEE 802.3bp and Open Alliance compliant automotive 1000Base-T1 Ethernet physical layer transceiver. The DP83TG721-Q1 provides all physical layer functions needed to transmit and receive data over unshielded/shielded single twisted-pair cables. The device provides xMII flexibility with support for RGMII and SGMII MAC interfaces.
DP83TG721-Q1 supports OA TC10 low-power sleep feature (with wake forwarding) to reduce system power consumption when communication is not required. This device offers the Diagnostic Tool Kit, with an extensive list of real-time monitoring tools, debug tools and test modes.
DP83TG721-Q1 integrates IEEE 1588v2/802.1AS hardware time stamping and fractional PLL enabling highly accurate time synchronization. The fractional PLL enables frequency/phase synchronization of the Wall Clock eliminating need for external VCXO and generating wide range of time synchronized frequencies needed for Audio, Video and other ADAS applications.
DP83TG721-Q1 also integrates IEEE 1722 CRF decode to generate Media Clock (wall clock synchronized) for AVB and other Audio standards. The DP83TG721-Q1 is also capable of generating FSYNC/SCLK (wall clock synchronized) for I2S/TDM8 interface needed for audio applications.
The DP83TG721-Q1 is compatible to TI’s 100BASE-T1 PHYs and 1000BASE-T1 PHYs enabling design scalability with single board for both speeds.
추가 정보 요청
전체 데이터 시트를 사용할 수 있습니다. 지금 요청
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DP83TG721x-Q1 Short | PDF | HTML | 2026. 9. 25 | |
| Application brief | Advancing Humanoid Robotics with Single Pair Ethernet | PDF | HTML | 2024. 12. 13 | ||
| 애플리케이션 노트 | Basic Ethernet Interface Debug With Linux | PDF | HTML | 2024. 10. 11 | ||
| 애플리케이션 노트 | How to Integrate Linux Driver Into Your System | PDF | HTML | 2024. 7. 12 | ||
| 인증서 | DP83TG721EVM-MC EU RoHS Declaration of Conformity (DoC) | 2022. 11. 4 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DP83TG721EVM-MC — DP83TG721 1000Base-T1~1000Base-T 미디어 컨버터 평가 모듈
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| VQFN (RHA) | 36 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.