계산 툴
BLDC-MAX-QG-MOSFET-CALCULATOR — Calculate the maximum QG MOSFET for your motor driver
Calculate the maximum QG MOSFET that can be driven based on the PWM switching frequency, algorithm type, and additional external capacitance.
DRV8353M
- 9 to 100-V, Triple half-bridge gate driver
-
Extended TA operation -55 °C to 125 °C
- Optional triple low-side current shunt amplifiers
-
- Smart gate drive architecture
- Adjustable slew rate control for EMI performance
- VGS handshake and minimum dead-time insertion to prevent shoot-through
- 50-mA to 1-A peak source current
- 100-mA to 2-A peak sink current
- dV/dt mitigation through strong pulldown
- Integrated gate driver power supplies
- High-side doubler charge pump For 100% PWM duty cycle control
- Low-side linear regulator
- Integrated triple current shunt amplifiers
- Adjustable gain (5, 10, 20, 40 V/V)
- Bidirectional or unidirectional support
- 6x, 3x, 1x, and independent PWM modes
- Supports 120° sensored operation
- SPI or hardware interface available
- Low-power sleep mode (20 µA at VVM = 48-V)
- Integrated protection features
- VM undervoltage lockout (UVLO)
- Gate drive supply undervoltage (GDUV)
- MOSFET VDS overcurrent protection (OCP)
- MOSFET shoot-through prevention
- Gate driver fault (GDF)
- Thermal warning and shutdown (OTW/OTSD)
- Fault condition indicator (nFAULT)
The DRV8353M family of devices are highly-integrated gate drivers for three-phase brushless DC (BLDC) motor applications. These applications include field-oriented control (FOC), sinusoidal current control, and trapezoidal current control of BLDC motors. The device variants provide optional integrated current shunt amplifiers to support different motor control schemes and a buck regulator to power the gate driver or external controller.
The DRV8353M uses smart gate drive (SGD) architecture to decrease the number of external components that are typically necessary for MOSFET slew rate control and protection circuits. The SGD architecture also optimizes dead time to prevent shoot-through conditions, provides flexibility in decreasing electromagnetic interference (EMI) by MOSFET slew rate control, and protects against gate short circuit conditions through VGS monitors. A strong gate pulldown circuit helps prevent unwanted dV/dt parasitic gate turn on events
Various PWM control modes (6x, 3x, 1x, and independent) are supported for simple interfacing to the external controller. These modes can decrease the number of outputs required of the controller for the motor driver PWM control signals. This family of devices also includes 1x PWM mode for simple sensored trapezoidal control of a BLDC motor by using an internal block commutation table.
기술 자료
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1개 모두 보기 | 유형 | 직함 | 날짜 | ||
|---|---|---|---|---|
| * | Data sheet | DRV8353M 100-V Three-Phase Smart Gate Driver datasheet | PDF | HTML | 2020/03/31 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
평가 보드
DRV8353RH-EVM — DRV8353RH 3상 스마트 게이트 드라이버 평가 모듈
The DRV8353RH-EVM is a 15A, 3-phase brushless DC drive stage based on the DRV8353RH gate driver and CSD19532Q5B NexFET™ MOSFETs.
The module has individual DC bus and phase voltage sense as well as individual low-side current shunt amplifiers, making this evaluation module ideal for sensorless BLDC (...)
사용 설명서: PDF
평가 보드
DRV8353RS-EVM — DRV8353RS 3상 스마트 게이트 드라이버 평가 모듈
The DRV8353RS-EVM is a 15A, 3-phase brushless DC drive stage based on the DRV8353RS gate driver and CSD19532Q5B NexFET™ MOSFETs.
The module has individual DC bus and phase voltage sense as well as individual low-side current shunt amplifiers, making this evaluation module ideal for sensorless BLDC (...)
사용 설명서: PDF
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| WQFN (RTA) | 40 | Ultra Librarian |
주문 및 품질
포함된 정보:
- RoHS
- REACH
- 디바이스 마킹
- 납 마감/볼 재질
- MSL 등급/피크 리플로우
- MTBF/FIT 예측
- 물질 성분
- 인증 요약
- 지속적인 신뢰성 모니터링
포함된 정보:
- 팹 위치
- 조립 위치