DS90CR286AT-Q1
- 20 to 66 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Setup & Hold Times on
Rx Outputs - Rx Power Consumption < 270 mW (typ)
at 66 MHz Worst Case - Rx Power-down Mode < 200 μW (max)
- ESD Rating: 4 kV (HBM), 1 kV (CDM)
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin DGG (TSSOP) Package
- Operating Temperature: −40°C to +105°C
- Automotive AEC-Q100 Grade 2 Qualified
The DS90CR286AT-Q1 receiver converts four LVDS (Low Voltage Differential Signaling) data streams back into parallel 28 bits of LVCMOS data. The receiver data outputs strobe on the output clock's rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The DS90CR286AT-Q1 phase-locks to the input LVDS clock, samples the serial bit streams at the LVDS data lines, and converts them into 28-bit parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps.
The DS90CR286AT-Q1 device is enhanced over prior generation receivers due to a wider data valid time on the receiver output. The DS90CR286AT-Q1 is designed for PCB board chip-to-chip OpenLDI-to-RGB bridge conversion. LVDS data transmission over cable interconnect is not recommended for this device.
Users designing a sub-system with a compatible OpenLDI transmitter and DS90CR286AT-Q1 receiver must ensure an acceptable skew margin budget (RSKM). Details regarding RSKM can be found in the Application Information section.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90CR286AT-Q1 3.3 V Rising Edge Data Strobe LVDS Receiver 28-Bit Channel Link 66 MHz datasheet (Rev. A) | PDF | HTML | 2015. 12. 6 | |
| 애플리케이션 노트 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018. 11. 9 | |||
| 애플리케이션 노트 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016. 1. 13 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
DS90CR285-86ATQEVM — DS90CR285 및 DS90CR286AT-Q1 채널 링크 I SerDes 평가 모듈
FLINK3V8BT-85 — 시리얼라이저 및 디시리얼라이저 LVDS 장치의 FPD-Link 제품군용 평가 키트
The FPD-Link evaluation kit includes a transmitter (Tx) board, a receiver (Rx) board and interfacing cables. This kit shows the chipsets interfacing from test equipment or a graphics controller using low-voltage differential signaling (LVDS) to a receiver board.
The transmitter board accepts (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.