DS90UR241
- Supports displays with 18-bit color depth
- 5MHz to 43MHz Pixel clock
- Automotive-grade product AEC-Q100 grade 2 qualified
- 24:1 Interface compression
- Embedded clock with DC balancing supports AC-coupled data transmission
- Capable to drive up to 10 meters shielded twisted-pair cable
- No reference clock required (deserializer)
- Meets ISO 10605 ESD – greater than 8kV HBM ESD structure
- Hot plug support
- EMI reduction – serializer accepts spread spectrum input; data randomization and shuffling on serial link; deserializer provides adjustable PTO (Progressive Turnon) LVCMOS outputs
- @Speed BIST (Built-In Self-Test) to validate LVDS transmission path
- Individual power-down controls for both transmitter and receiver
- Power supply range 3.3V ±10%
- 48-pin TQFP package for transmitter and 64-pin TQFP package for receiver
- Temperature range: –40°C to 105°C
- Backward-compatible mode with DS90C241/DS90C124
The DS90URxxx-Q1 chipset translates a 24-bit parallel bus into a fully transparent data/control FPD-Link II LVDS serial stream with embedded clock information. This chipset is designed for driving graphical data to displays requiring 18-bit color depth: RGB666 + HS, VS, DE + three additional general-purpose data channels. This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. The device saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins.
The DS90URxxx-Q1 incorporates FPD-Link II LVDS signaling on the high-speed I/O. FPD-Link II LVDS provides a low-power and low-noise environment for reliably transferring data over a serial transmission path. By optimizing the Serializer output edge rate for the operating frequency range, EMI is further reduced.
In addition, the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC-balanced encoding and decoding is used to support AC-coupled interconnects. Using TI’s proprietary random lock, the parallel data of the Serializer are randomized to the Deserializer without the need of REFCLK.
관심 가지실만한 유사 제품
비교 대상 장치와 유사한 기능.
기술 자료
| 상위 문서 | 유형 | 직함 | 형식 옵션 | 최신 영어 버전 다운로드 | 날짜 |
|---|---|---|---|---|---|
| * | 데이터 시트 | DS90URxxx-Q1 5MHz to 43MHz DC-Balanced 24-Bit FPD-Link II Serializer and Deserializer Chipset datasheet (Rev. P) | PDF | HTML | 2024. 8. 29 | |
| 애플리케이션 노트 | LVDS Repeaters and Crosspoints Extend the Reach of FPD-Link II Interfaces (Rev. A) | 2013. 4. 29 | |||
| 애플리케이션 노트 | DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E) | 2013. 4. 29 | |||
| 애플리케이션 노트 | Extending the Reach of a FPD-Link II Interface with Cable Drivers and Equalizers (Rev. A) | 2013. 4. 26 | |||
| 애플리케이션 노트 | AN-2068 DS90UR241/124 Spread Spectrum Tolerance Support (Rev. B) | 2013. 4. 26 | |||
| 애플리케이션 노트 | AN-1807 FPD-Link II Display SerDes Overview (Rev. B) | 2013. 4. 26 | |||
| 사용 설명서 | High Efficiency Portable Media Player (PMP) Dock Station User Guide | 2012. 1. 27 | |||
| 사용 설명서 | DS90UR241/DS90UR124 SERDES Evaluation Kit User's Guide | 2012. 1. 26 |
설계 및 개발
추가 조건 또는 필수 리소스는 사용 가능한 경우 아래 제목을 클릭하여 세부 정보 페이지를 확인하세요.
SERDESUR-43USB — DS90UR241 DS90UR124 시리얼라이저 및 디시리얼라이저 칩셋용 평가 키트
The SERDESUR-43 is an evaluation kit designed to demonstrate performance and capabilities of the DS90UR124 and DS90UR241 FPD-Link II Serializer/Deserializer Chipset.
The DS90UR241 Serializer board accepts LVCMOS input signals and provides single serialized FPD-LInk II LVDS data pair as an output. (...)
| 패키지 | 핀 | CAD 기호, 풋프린트 및 3D 모델 |
|---|---|---|
| TQFP (PFB) | 48 | Ultra Librarian |
주문 및 품질
권장 제품에는 본 TI 제품과 관련된 매개 변수, 평가 모듈 또는 레퍼런스 디자인이 있을 수 있습니다.